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Technology innovations for smart cities 智慧城市的技术创新
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243763
Akira Maeda
{"title":"Technology innovations for smart cities","authors":"Akira Maeda","doi":"10.1109/VLSIC.2012.6243763","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243763","url":null,"abstract":"New technologies are required in smart city applications, such as sensing, highly parallel processing, and mobile broadband communication. In this paper, it is pointed out that integration of information and control system technologies will be a key driver for smart cities, because these systems with quite different system characteristics should be integrated to realize sophisticated social infrastructure systems. Our approach will be explained with several project examples to describe the challenges and future trend of technology development.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"40 1","pages":"6-9"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79168019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from −50°C to +150°C using piecewise-linear-current curvature compensation 采用分段线性电流曲率补偿的sub-1V 3.9µW带隙基准，在−50°C至+150°C范围内的3σ误差为±0.34%
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243770
S. Sano, Yasuhiko Takahashi, M. Horiguchi, M. Ota
{"title":"A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from −50°C to +150°C using piecewise-linear-current curvature compensation","authors":"S. Sano, Yasuhiko Takahashi, M. Horiguchi, M. Ota","doi":"10.1109/VLSIC.2012.6243770","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243770","url":null,"abstract":"A sub-1V 3.9μW bandgap reference (BGR) with small voltage variation of ±0.34% and low temperature drift (1mV) over a wide temperature range (-50°C ~ +150°C) and a wide voltage range (+0.9 V ~ +5.5V) by using a low power current mode BGR core and a piecewise-linear curvature compensation system. The BGR occupies 0.1mm<sup>2</sup> in 0.13μm CMOS technology with triple well structure.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"22-23"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85542030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS 4×12 Gb/s 0.96 pJ/b/lane模拟- iir串扰对消和信号复用接收器，用于65nm CMOS单端I/ o
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243829
Taehyoun Oh, R. Harjani
{"title":"4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS","authors":"Taehyoun Oh, R. Harjani","doi":"10.1109/VLSIC.2012.6243829","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243829","url":null,"abstract":"A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"140-141"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81754866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS 全0.5V, 1Mbps, 315MHz OOK收发器，38µW无职业频率间歇采样接收器和52µW 40 nm CMOS f类发射器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243778
Akira Saito, Kentaro Honda, Y. Zheng, S. Iguchi, Kazunori Watanabe, T. Sakurai, M. Takamiya
{"title":"An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS","authors":"Akira Saito, Kentaro Honda, Y. Zheng, S. Iguchi, Kazunori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2012.6243778","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243778","url":null,"abstract":"An all 0.5V, 1Mbps, 315MHz OOK transceiver in 40-nm CMOS for body area networks is developed. Both a 38-pJ/bit career-frequency-free intermittent sampling receiver with -55dBm sensitivity and a 52-pJ/bit class-F transmitter with -21dBm output power achieve the lowest energy in the published transceivers for wireless sensor networks.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"37 1","pages":"38-39"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85807429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices 克服移动设备中d类音频放大器限制的电路技术
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243768
Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, S. Arunachalam, T. Brooks
{"title":"Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices","authors":"Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, S. Arunachalam, T. Brooks","doi":"10.1109/VLSIC.2012.6243768","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243768","url":null,"abstract":"Circuit techniques to overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4V achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on over-limit current events.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"34 1","pages":"18-19"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79075095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs 通过柔性电子器件与高性能集成电路的可扩展接口，用于结构健康监测的高分辨率传感片
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243819
Yingzhe Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. Sturm, S. Wagner, N. Verma
{"title":"High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs","authors":"Yingzhe Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. Sturm, S. Wagner, N. Verma","doi":"10.1109/VLSIC.2012.6243819","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243819","url":null,"abstract":"Early-stage damage detection for buildings and bridges requires continuously sensing and assessing strain over large surfaces, yet with centimeter-scale resolution. To achieve this, we present a sensing sheet that combines high-performance ICs with flexible electronics, allowing bonding to such surfaces. The flexible electronics integrates thin-film strain gauges and amorphous-silicon control circuits, patterned on a polyimide sheet that can potentially span large areas. Non-contact links couple digital and analog signals to the ICs, allowing many ICs to be introduced via low-cost sheet lamination for energy-efficient readout and computation over a large number of sensors. Communication between distributed ICs is achieved by transceivers that exploit low-loss interconnects patterned on the polyimide sheet; the transceivers self-calibrate to the interconnect impedance to maximize transmit SNR. The system achieves multi-channel strain readout with sensitivity of 18μStrainRMS at an energy per measurement of 270nJ, while the communication energy is 12.8pJ/3.3pJ per bit (Tx/Rx) over 7.5m.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"93 1","pages":"120-121"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76276232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOS 21.5mW 10+Gb/s毫米波相控阵发射机65nm CMOS
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243785
Lingkai Kong, E. Alon
{"title":"A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOS","authors":"Lingkai Kong, E. Alon","doi":"10.1109/VLSIC.2012.6243785","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243785","url":null,"abstract":"This paper presents a 65nm mm-wave transmitter efficiently supporting QPSK modulation and phased array functionality with a proposed oscillator modulation technique. The design delivers an average output power of 1mW at 10Gb/s and 0.8mW at 14Gb/s while consuming 21.5mA DC current from a 1V supply. At 10Gb/s, an overall transmitter efficiency of 4.65% is achieved, representing ~1.8X improvement over prior art [1].","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"13 1","pages":"52-53"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73451055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS 采用28nm CMOS的宽共模全自适应多标准12.5Gb/s背板收发器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243811
J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang
{"title":"A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS","authors":"J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang","doi":"10.1109/VLSIC.2012.6243811","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243811","url":null,"abstract":"This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"4 1","pages":"104-105"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73862377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM 采用免刷新嵌入式DRAM实现的1.6 mm2 38mw 1.5 gb /s LDPC解码器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243816
Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang
{"title":"A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM","authors":"Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang","doi":"10.1109/VLSIC.2012.6243816","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243816","url":null,"abstract":"Memory dominates the power consumption of high-throughput LDPC decoders. A 700 MHz refresh-free embedded DRAM (eDRAM) is designed as a low-power memory to retain data for the required access window. 321-kb eDRAM arrays are integrated in a 1.6 mm2, 65nm LDPC decoder suitable for IEEE 802.11ad. The LDPC decoder consumes 38 mW for a 1.5 Gb/s throughput at 90 MHz and 10 decoding iterations, and it achieves up to 9 Gb/s at 540 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"32 1","pages":"114-115"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74640723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC 34fj10b 500 MS/s部分交错流水线SAR ADC
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243804
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins
{"title":"A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC","authors":"Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/VLSIC.2012.6243804","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243804","url":null,"abstract":"A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"95 1","pages":"90-91"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73559669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
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