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2012 Symposium on VLSI Circuits (VLSIC)最新文献

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An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS 全0.5V, 1Mbps, 315MHz OOK收发器，38µW无职业频率间歇采样接收器和52µW 40 nm CMOS f类发射器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243778
Akira Saito, Kentaro Honda, Y. Zheng, S. Iguchi, Kazunori Watanabe, T. Sakurai, M. Takamiya
{"title":"An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS","authors":"Akira Saito, Kentaro Honda, Y. Zheng, S. Iguchi, Kazunori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2012.6243778","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243778","url":null,"abstract":"An all 0.5V, 1Mbps, 315MHz OOK transceiver in 40-nm CMOS for body area networks is developed. Both a 38-pJ/bit career-frequency-free intermittent sampling receiver with -55dBm sensitivity and a 52-pJ/bit class-F transmitter with -21dBm output power achieve the lowest energy in the published transceivers for wireless sensor networks.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"37 1","pages":"38-39"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85807429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS 4×12 Gb/s 0.96 pJ/b/lane模拟- iir串扰对消和信号复用接收器，用于65nm CMOS单端I/ o
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243829
Taehyoun Oh, R. Harjani
{"title":"4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS","authors":"Taehyoun Oh, R. Harjani","doi":"10.1109/VLSIC.2012.6243829","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243829","url":null,"abstract":"A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"140-141"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81754866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Technology innovations for smart cities 智慧城市的技术创新
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243763
Akira Maeda
{"title":"Technology innovations for smart cities","authors":"Akira Maeda","doi":"10.1109/VLSIC.2012.6243763","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243763","url":null,"abstract":"New technologies are required in smart city applications, such as sensing, highly parallel processing, and mobile broadband communication. In this paper, it is pointed out that integration of information and control system technologies will be a key driver for smart cities, because these systems with quite different system characteristics should be integrated to realize sophisticated social infrastructure systems. Our approach will be explained with several project examples to describe the challenges and future trend of technology development.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"40 1","pages":"6-9"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79168019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A standard cell compatible bidirectional repeater with thyristor assist 标准单元兼容双向中继器与晶闸管辅助
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243846
Sudhir K. Satpathy, D. Sylvester, D. Blaauw
{"title":"A standard cell compatible bidirectional repeater with thyristor assist","authors":"Sudhir K. Satpathy, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2012.6243846","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243846","url":null,"abstract":"A thyristor-assisted standard cell compatible self-timed bidirectional repeater with no configuration overhead enables 8mm interconnects to achieve 37% higher speed at 20% lower energy over conventional repeaters in 65nm CMOS at 1.0V. Bidirectional operation without the need for configuration logic removes the need for clocking, yielding up to 14× higher energy efficiency at low data switching activity.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"64 1","pages":"174-175"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73832449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS 基于32nm CMOS的2.8GHz 128入口× 152b 3读2写多精度浮点寄存器文件和shuffle
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243818
S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar
{"title":"A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS","authors":"S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2012.6243818","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243818","url":null,"abstract":"A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"278 1","pages":"118-119"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83428208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW 一种0.45 v输入片上栅极升压(OGB) 40纳米CMOS降压变换器，在2µW至50µW负载范围内效率超过90%
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243856
Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya
{"title":"A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW","authors":"Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2012.6243856","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243856","url":null,"abstract":"A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"44 1","pages":"194-195"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80151595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOS 21.5mW 10+Gb/s毫米波相控阵发射机65nm CMOS
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243785
Lingkai Kong, E. Alon
{"title":"A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOS","authors":"Lingkai Kong, E. Alon","doi":"10.1109/VLSIC.2012.6243785","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243785","url":null,"abstract":"This paper presents a 65nm mm-wave transmitter efficiently supporting QPSK modulation and phased array functionality with a proposed oscillator modulation technique. The design delivers an average output power of 1mW at 10Gb/s and 0.8mW at 14Gb/s while consuming 21.5mA DC current from a 1V supply. At 10Gb/s, an overall transmitter efficiency of 4.65% is achieved, representing ~1.8X improvement over prior art [1].","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"13 1","pages":"52-53"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73451055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS 采用28nm CMOS的宽共模全自适应多标准12.5Gb/s背板收发器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243811
J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang
{"title":"A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS","authors":"J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang","doi":"10.1109/VLSIC.2012.6243811","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243811","url":null,"abstract":"This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"4 1","pages":"104-105"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73862377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM 采用免刷新嵌入式DRAM实现的1.6 mm2 38mw 1.5 gb /s LDPC解码器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243816
Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang
{"title":"A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM","authors":"Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang","doi":"10.1109/VLSIC.2012.6243816","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243816","url":null,"abstract":"Memory dominates the power consumption of high-throughput LDPC decoders. A 700 MHz refresh-free embedded DRAM (eDRAM) is designed as a low-power memory to retain data for the required access window. 321-kb eDRAM arrays are integrated in a 1.6 mm2, 65nm LDPC decoder suitable for IEEE 802.11ad. The LDPC decoder consumes 38 mW for a 1.5 Gb/s throughput at 90 MHz and 10 decoding iterations, and it achieves up to 9 Gb/s at 540 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"32 1","pages":"114-115"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74640723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC 34fj10b 500 MS/s部分交错流水线SAR ADC
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243804
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins
{"title":"A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC","authors":"Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/VLSIC.2012.6243804","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243804","url":null,"abstract":"A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"95 1","pages":"90-91"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73559669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
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