采用免刷新嵌入式DRAM实现的1.6 mm2 38mw 1.5 gb /s LDPC解码器

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243816

Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang

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引用次数: 25

摘要

内存在高吞吐量LDPC解码器的功耗中占主导地位。700mhz免刷新嵌入式DRAM (eDRAM)设计为低功耗存储器，为所需的访问窗口保留数据。321kb的eDRAM阵列集成在1.6 mm2、65nm LDPC解码器中，适用于IEEE 802.11ad。LDPC解码器在90 MHz和10次解码迭代时的吞吐量为1.5 Gb/s，功耗为38 mW，在540 MHz时可达到9gb /s。

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A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM

Memory dominates the power consumption of high-throughput LDPC decoders. A 700 MHz refresh-free embedded DRAM (eDRAM) is designed as a low-power memory to retain data for the required access window. 321-kb eDRAM arrays are integrated in a 1.6 mm2, 65nm LDPC decoder suitable for IEEE 802.11ad. The LDPC decoder consumes 38 mW for a 1.5 Gb/s throughput at 90 MHz and 10 decoding iterations, and it achieves up to 9 Gb/s at 540 MHz.

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2012 Symposium on VLSI Circuits (VLSIC)

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