J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang
{"title":"A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS","authors":"J. Savoj, K. Hsieh, P. Upadhyaya, F. An, Ade Bekele, S. Chen, Xuewen Jiang, K. Lai, Chi Fung Poon, Aman Sewani, D. Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, E. Alon, Ken Chang","doi":"10.1109/VLSIC.2012.6243811","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"4 1","pages":"104-105"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
Abstract
This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10-15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
