34fj10b 500 MS/s部分交错流水线SAR ADC

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243804

Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins

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引用次数: 32

摘要

提出了一种10b 500MS/s的ADC，该ADC前端共享一个高速SAR，并与共享运放和二级SAR ADC相交叉，实现了高速、低功耗和小面积。该原型ADC采用65nm CMOS，在1.2V电压下，平均SNDR为55.4dB，功耗为8.2mW。包括偏置校准在内的活动模具面积为0.046mm2。

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A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC

A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.

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2012 Symposium on VLSI Circuits (VLSIC)

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