Isolated Preset Architecture for a 32nm SOI embedded DRAM macro

Abstract

The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.