Microprocessors and Microsystems最新文献_第6页

Retraction notice to the articles published in the Special issue Embedded Processors from “Microprocessors and Microsystems” 关于 "微处理器与微系统 "特刊 "嵌入式处理器 "中发表文章的撤稿通知

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-09 DOI: 10.1016/j.micpro.2024.105019

引用次数: 0

Retraction notice to the articles published in the Special issue Internet of People from “Microprocessors and Microsystems” 从 "微处理器和微系统 "撤下发表在《Internet of People》特刊上的文章的通知

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-09 DOI: 10.1016/j.micpro.2024.105020

引用次数: 0

Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital 在 FPGA 上对 Western Digital 公司的 COTS RISC-V VeeR EH1 软处理器的 SEU 敏感性进行非侵入式研究

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-01 DOI: 10.1016/j.micpro.2024.105021

Daniel León , Juan Carlos Fabero , Juan A. Clemente

{"title":"Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital","authors":"Daniel León , Juan Carlos Fabero , Juan A. Clemente","doi":"10.1016/j.micpro.2024.105021","DOIUrl":"10.1016/j.micpro.2024.105021","url":null,"abstract":"<div><p>This article studies the ISA-extension and application-specific soft error sensitivity of the RISC-V VeeR EH1 commercial processor core from Western Digital. To this end, a modified VeeRwolf SoC from Chips Alliance was deployed in a Digilent Nexys-A7 FPGA. Then, a fault injection platform was created for injecting soft errors in all architectural and micro-architectural registers of the VeeR EH1, without modifying the original processor core, when executing a set of commonly used space-related algorithms. Errors were categorized according to the consequences that they had on the normal execution of the processor, as well as to the unit of the core they were injected in. By changing compiling targets, four different combinations of RISC-V ISA extensions were also tested and compared, in the same processor IP, for a typical dot product algorithm, a hyperspectral imaging difference calculation and a SHA-256 hash. Experimental results will show how, for each one of these three case studies, the functionally equal binaries issued when compiling these programs using different ISA extensions are affected in different ways by error injections, opening the possibility to selectively compile functions based on a desired reliability/speed factor. The results additionally identify the specific units and subUnits within the processor’s structure that have been affected, pinpointing the exact element where the bitflip occurred, after detecting an error.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105021"},"PeriodicalIF":2.6,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933124000164/pdfft?md5=6cda82c9e092425830b84a3606e69664&pid=1-s2.0-S0141933124000164-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139663949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications 5G+ 和生物医学应用中的新型混合快速傅立叶变换处理器

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-26 DOI: 10.1016/j.micpro.2024.105022

R. Priyadharsini, S. Sasipriya

{"title":"A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications","authors":"R. Priyadharsini, S. Sasipriya","doi":"10.1016/j.micpro.2024.105022","DOIUrl":"10.1016/j.micpro.2024.105022","url":null,"abstract":"<div><p>To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mn>2</mn></msup></mrow></math></span>), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105022"},"PeriodicalIF":2.6,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139588661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parametrized low-complexity hardware architecture of an H.264-based video encoder for FPGAs 基于 H.264 的 FPGA 视频编码器的参数化低复杂度硬件架构

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-13 DOI: 10.1016/j.micpro.2024.105017

Azam Tayyebi , Darrin Hanna , Bryant Jones

引用次数: 0

FPGA-based remote target classification in hyperspectral imaging using multi-graph neural network 利用多图神经网络在高光谱成像中进行基于 FPGA 的远程目标分类

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-13 DOI: 10.1016/j.micpro.2024.105008

C Chellaswamy, M Muthu Manjula, B Ramasubramanian, A Sriram

{"title":"FPGA-based remote target classification in hyperspectral imaging using multi-graph neural network","authors":"C Chellaswamy, M Muthu Manjula, B Ramasubramanian, A Sriram","doi":"10.1016/j.micpro.2024.105008","DOIUrl":"10.1016/j.micpro.2024.105008","url":null,"abstract":"<div><p>Hyperspectral imagery (HSI) is widely used in remote sensing for target classification; however, its accurate classification remains challenging due to the scarcity of labeled data. Graph Neural Networks (GNNs) have emerged as a popular method for semi-supervised classification, attracting significant interest in the context of HSI analysis. Nevertheless, conventional GNN-based approaches often rely on a single graph filter to extract HSI characteristics, failing to fully exploit the potential benefits of different graph filters. Additionally, oversmoothing issues plague classical GNNs, further affecting classification performance. To address these drawbacks, we propose a novel approach called Spectral and Autoregressive Moving Average Graph Filter for the Multi-Graph Neural Network (SAM-GNN). This approach leverages two distinct graph filters: one specialized in extracting the spectral characteristics of nodes and the other effectively suppressing graph distortion. Through extensive evaluations, we compare the performance of SAM-GNN with other state-of-the-art methods, employing metrics such as overall accuracy (OA), individual class accuracy (IA), and Kappa coefficient (KC). The results shows that the SAM-GNN provides an improvement in KC, IA, and OA of 6.71%, 5.7%, and 3.93% for the Pavia University dataset and 4.67%, 3.67%, and 3.49% for the Cuprite dataset respectively. Furthermore, we implement SAM-GNN on the Virtex-7 field-programmable gate array (FPGA), demonstrating that the method achieves highly accurate target localization results, bringing us closer to real-world applications in HSI classification.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105008"},"PeriodicalIF":2.6,"publicationDate":"2024-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139462263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA-friendly compact and efficient AES-like 8 × 8 S-box 适合 FPGA 的紧凑高效 AES 类 8 × 8 S-box

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-08 DOI: 10.1016/j.micpro.2024.105007

Ahmet Malal , Cihangir Tezcan

{"title":"FPGA-friendly compact and efficient AES-like 8 × 8 S-box","authors":"Ahmet Malal , Cihangir Tezcan","doi":"10.1016/j.micpro.2024.105007","DOIUrl":"10.1016/j.micpro.2024.105007","url":null,"abstract":"<div><p><span>One of the main layers in the Advanced Encryption Standard (AES) is the substitution layer, where an 8 × 8 S-Box is used 16 times. The substitution layer provides confusion and makes the algorithm resistant to </span>cryptanalysis<span> techniques. Therefore, the security of the algorithm is also highly dependent on this layer. However, the cost of implementing 8 × 8 S-Box on FPGA platforms is considerably higher than other layers of the algorithm. Since S-Boxes are repeatedly used in the algorithm, the cost of the algorithm highly comes from the substitution layer. In 2005, Canright used different extension fields to represent AES S-Box to get FPGA-friendly compact designs. The best optimization proposed by Canright reduced the gate-area of the AES S-Box implementation by 20%.</span></p><p><span>In this study, we use the same optimization methods that Canright used to optimize AES S-Box on hardware platforms. Our purpose is not to optimize AES S-Box; we aim to create another 8 × 8 S-Box which is strong and compact enough for FPGA platforms. We create an 8 × 8 S-Box using the inverse field operation as in the case of AES S-Box. We use another irreducible polynomial to represent the finite field and get an FPGA-friendly compact and efficient 8 × 8 S-Box. The finite field we propose provides the same level of security against cryptanalysis techniques with a 3.125% less gate-area on Virtex-7 and Artix-7 FPGAs compared to Canright’s results. Moreover, our proposed S-Box requires 11.76% less gate on Virtex-4 FPGAs. These gate-area improvements are beneficial for resource-constraint </span>IoT<span> devices and allow more copies of the S-Box for algorithm parallelism. Therefore, we claim that our proposed S-Box is more compact and efficient than AES S-Box. Cryptographers who need an 8 × 8 S-Box can use our proposed S-Box in their designs instead of AES S-Box with the same level of security but better efficiency.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105007"},"PeriodicalIF":2.6,"publicationDate":"2024-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139457675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Model-based, fully simulated, system-level power consumption estimation of IoT devices 基于模型、完全仿真的物联网设备系统级功耗估算

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-08 DOI: 10.1016/j.micpro.2024.105009

Özen Özkaya , Berna Örs

{"title":"Model-based, fully simulated, system-level power consumption estimation of IoT devices","authors":"Özen Özkaya , Berna Örs","doi":"10.1016/j.micpro.2024.105009","DOIUrl":"10.1016/j.micpro.2024.105009","url":null,"abstract":"<div><p>Internet of things<span><span> (IoT) gaining more importance due to its crucial role in pervasive computing<span> and also Industry 4.0. Since the number of IoT devices is scaling up to multiple dozens of billions, the importance of energy efficiency is significantly increased. With the consideration of huge variety of IoT device hardware and software, a comprehensive model and estimation methodology on energy consumption is necessary as an enabler. IoT devices are also frequently updated, upgraded and maintained because of the evolving nature of the requirements and market demands. Each and every such operation has an effect on the </span></span>power consumption<span><span> and arose the necessity for a new energy consumption modeling and estimation. This process is applicable for development of IoT devices, as well as the maintenance phase. Since the variety of designs is unlimited, and battery capacity is usually fixed, or a cost factor, a generic, fully simulated, model-based energy consumption estimation of IoT devices is crucial. In this study, we aim to address this problem via proposing fully simulated, model-based, system-level power estimation approaches, as well as their success rate in typical real-life scenarios. It can be seen that the proposed methodology has high accuracy over %97. For the realization of the best-proposed approach, we used Open Virtual Platform (OVP) as an instruction set </span>accurate simulator.</span></span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105009"},"PeriodicalIF":2.6,"publicationDate":"2024-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139397954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices 边缘分拣机：用于面积和功耗受限的边缘计算设备的硬件分拣引擎

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-05 DOI: 10.1016/j.micpro.2024.105006

Hakem Beitollahi , Marziye Pandi , Mostafa Moghaddas

{"title":"Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices","authors":"Hakem Beitollahi , Marziye Pandi , Mostafa Moghaddas","doi":"10.1016/j.micpro.2024.105006","DOIUrl":"10.1016/j.micpro.2024.105006","url":null,"abstract":"<div><p><span><span>In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded </span>edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low </span>power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105006"},"PeriodicalIF":2.6,"publicationDate":"2024-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139375497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Retraction notice to “real-time monitoring of the athlete's musculoskeletal health based on an embedded processor” [Microprocessors and Microsystems 81 (2021) 103742] 基于嵌入式处理器的运动员肌肉骨骼健康实时监测 "的撤稿通知 [Microprocessors and Microsystems 81 (2021) 103742]

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-01-04 DOI: 10.1016/j.micpro.2023.104997

Rongjun Zhu

引用次数: 0