Microprocessors and Microsystems最新文献

{"title":"Real-time neural network-based thermal stress compensation for pressure sensors in precision localization systems","authors":"Paola Vitolo ,&nbsp;Rosalba Liguori ,&nbsp;Luigi Di Benedetto ,&nbsp;Alfredo Rubino ,&nbsp;Danilo Pau ,&nbsp;Gian Domenico Licciardo","doi":"10.1016/j.micpro.2025.105183","DOIUrl":"10.1016/j.micpro.2025.105183","url":null,"abstract":"<div><div>This article presents a real-time Artificial Intelligence-based Reconfigurable Self-Calibration Unit (AI-ReSCU) for piezoresistive MEMS pressure sensors, designed to mitigate long-term drift effects induced by thermal stress. The system integrates a compact and reconfigurable neural network to dynamically estimate and correct sensor inaccuracies with minimal energy and area overhead. The architecture comprises a trigger module for detecting deviations from nominal behavior and a compensation engine driven by a quantized neural network optimized for hardware efficiency. The network processes temporal input windows and operates using 24-bit activations and 1-bit weights, enabling real-time inference with ultra-low power consumption. The fully digital system was prototyped in STMicroelectronics’ BCD8 technology, occupying 0.55 mm² and achieving a dynamic power consumption of 4.46 nW under typical conditions, thanks to extensive resource reuse and clock gating strategies. Offline experimental validation on LPS22HH pressure sensors demonstrated the system’s ability to recover up to 1.6 hPa of drift-induced error with a recovery latency of approximately 50 input samples, while maintaining measurement deviations within ±0.5 hPa across multiple stress scenarios.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105183"},"PeriodicalIF":1.9,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144633254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High throughput DLP and mixed radix based architectures of Viterbi decoder","authors":"Mohamed Asan Basiri M.","doi":"10.1016/j.micpro.2025.105181","DOIUrl":"10.1016/j.micpro.2025.105181","url":null,"abstract":"<div><div>Viterbi decoders play an important role in digital communication. This manuscript proposes two high throughput VLSI architectures of Viterbi decoder. In the first proposed architecture, the data level parallelism (DLP) based Viterbi decoder of rate <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mi>N</mi></mrow></mfrac></math></span> can be used to perform 1, 2, 4, 8, …parallel decodings of rates <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mi>N</mi></mrow></mfrac></math></span>, <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mrow><mo>(</mo><mi>N</mi><mo>/</mo><mn>2</mn><mo>)</mo></mrow></mrow></mfrac></math></span>, <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mrow><mo>(</mo><mi>N</mi><mo>/</mo><mn>4</mn><mo>)</mo></mrow></mrow></mfrac></math></span>, <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mrow><mo>(</mo><mi>N</mi><mo>/</mo><mn>8</mn><mo>)</mo></mrow></mrow></mfrac></math></span>, …respectively. The second proposed mixed radix Viterbi decoder architecture is to perform four numbers of radix-<span><math><msup><mrow><mn>2</mn></mrow><mrow><mi>k</mi><mo>−</mo><mn>1</mn></mrow></msup></math></span> decodings in parallel using one radix-<span><math><msup><mrow><mn>2</mn></mrow><mrow><mi>k</mi></mrow></msup></math></span> Viterbi decoder, where <span><math><mrow><mi>k</mi><mo>≥</mo><mn>1</mn></mrow></math></span>. All the conventional and proposed Viterbi decoders are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the proposed designs achieve high throughput as compared with the conventional designs. According to the synthesis results, the proposed mixed radix-2&amp;4 decoder achieves 73.9% of improvement in maximum throughput as compared with the conventional radix-4 design.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105181"},"PeriodicalIF":1.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High throughput event filtering: The interpolation-based DIF algorithm hardware architecture","authors":"Marcin Kowalczyk,&nbsp;Tomasz Kryjak","doi":"10.1016/j.micpro.2025.105171","DOIUrl":"10.1016/j.micpro.2025.105171","url":null,"abstract":"<div><div>In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105171"},"PeriodicalIF":1.9,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluating the performance of TinyML singular and ensemble techniques for intrusion detection in IoT networks","authors":"Abderahmane Hamdouchi ,&nbsp;Ali Idri","doi":"10.1016/j.micpro.2025.105172","DOIUrl":"10.1016/j.micpro.2025.105172","url":null,"abstract":"<div><div>As the Internet of Things (IoT) expands, safeguarding IoT networks from vulnerabilities becomes critical. Intrusion detection systems (IDS) leveraging machine learning (ML) techniques are essential for enhancing security and preventing unauthorized access. However, transmitting data to the cloud can introduce latency, impeding real-time attack detection. This research evaluates three TinyML ensemble techniques (random forest, XGBoost, and extra trees) and three singular techniques (decision tree, Gaussian naive Bayes, and multilayer perceptron) using two feature selection methods (maximum relevance minimum redundancy and analysis of variance) on the NF-ToN-IoT-v2 and NF-BoT-IoT-v2 datasets for cyberattack detection. Evaluations on the Arduino UNO used the prediction performance criteria (Cohen’s kappa and Matthew’s correlation coefficient), device metrics (latency, static RAM, and flash memory), and the Scott-Knott test and Borda count voting system to assess the statistical significance and to rank the models. Results show that singular TinyML models outperformed ensemble models for multiclass classification in the IDS-IoT context. The best models are: (1) MLP with 20 features and a hidden layer size of 56 for NF-ToN-IoT-v2; and (2) ET with 13 features, 2 estimators, and a tree depth of 16 for NF-BoT-IoT-v2.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105172"},"PeriodicalIF":1.9,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A reconfigurable PUF and TRNG design based on multiplexers for securing IoT applications","authors":"Zhiyuan Pan ,&nbsp;Jiafeng Cheng ,&nbsp;Nengyuan Sun ,&nbsp;Jinghe Wang ,&nbsp;Kai Shi ,&nbsp;Jianghong Li ,&nbsp;Zhaoyi Niu ,&nbsp;Jiaqi Wang ,&nbsp;Jiawei Zhang ,&nbsp;Linhan Wang ,&nbsp;Weize Yu","doi":"10.1016/j.micpro.2025.105170","DOIUrl":"10.1016/j.micpro.2025.105170","url":null,"abstract":"<div><div>Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) are two important hardware security primitives in modern cryptography. A regular arbiter PUF can be broken by machine learning (ML) attacks without much effort since a high linear relationship exists between the input data and the output response of the PUF. In this paper, an ML-resistant reconfigurable PUF and TRNG (RePT) architecture is proposed for the first time. Within this RePT design, a non-linearization technique by masking the linear relationship between the input data and the output response is proposed to greatly reinforce the robustness of an arbiter PUF against ML attacks without significantly increasing its area and power overhead. So as to further reuse the existing hardware resource within the arbiter PUF to build another hardware security primitive: TRNG, a novel algorithm is proposed to efficiently determine the selection signal value of each multiplexer within the arbiter PUF. As shown in the result, the proposed RePT design is able to achieve a 38 Mbps PUF (260 Mbps TRNG) throughput with 32,621 <span><math><mi>μ</mi></math></span>m<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> area, under the synthesis of SMIC 55 nm process design kits (PDK). Additionally, when ML attacks are performed on the proposed RePT circuit, it cannot be cracked even if 100,000 training data are enabled.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"116 ","pages":"Article 105170"},"PeriodicalIF":1.9,"publicationDate":"2025-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144189866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"STRATUM project: AI-based point of care computing for neurosurgical 3D decision support tools","authors":"Himar Fabelo ,&nbsp;Raquel Leon ,&nbsp;Emanuele Torti ,&nbsp;Santiago Marco ,&nbsp;Asaf Badouh ,&nbsp;Max Verbers ,&nbsp;Carlos Vega ,&nbsp;Javier Santana-Nunez ,&nbsp;Yann Falevoz ,&nbsp;Yolanda Ramallo-Fariña ,&nbsp;Christian Weis ,&nbsp;Ana M Wägner ,&nbsp;Eduardo Juarez ,&nbsp;Claudio Rial ,&nbsp;Alfonso Lagares ,&nbsp;Gustav Burström ,&nbsp;Francesco Leporati ,&nbsp;Luis Jimenez-Roldan ,&nbsp;Elisa Marenzi ,&nbsp;Teresa Cervero ,&nbsp;Gustavo M. Callico","doi":"10.1016/j.micpro.2025.105157","DOIUrl":"10.1016/j.micpro.2025.105157","url":null,"abstract":"<div><div>Integrated digital diagnostics are transforming complex surgical procedures, with brain tumour surgery being among the most challenging. STRATUM, a five-year Horizon Europe-funded project, aims to develop an advanced 3D decision support system leveraging real-time multimodal data processing powered by artificial intelligence. A key innovation of STRATUM is its design as an energy-efficient Point-of-Care computing system, seamlessly integrated into neurosurgical workflows. This system will provide surgeons with real-time, AI-driven insights, enhancing decision-making accuracy and efficiency. By optimizing surgical precision and reducing procedure duration, STRATUM is expected to improve patient outcomes while streamlining resource utilization within European healthcare systems.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"116 ","pages":"Article 105157"},"PeriodicalIF":1.9,"publicationDate":"2025-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AAL-based smart cane system with security and privacy features for blind and visually impaired individuals","authors":"Kyriaki Tsantikidou,&nbsp;Grigorios Delimpaltadakis,&nbsp;Damianos Diasakos,&nbsp;Nicolas Sklavos","doi":"10.1016/j.micpro.2025.105155","DOIUrl":"10.1016/j.micpro.2025.105155","url":null,"abstract":"<div><div>Ambient Assisted Living (AAL) technologies aim at increasing the quality of life for people with impairments. Practicality, reliability, autonomy, ease-of-use, safety, and low cost are of the utmost importance and in some cases omitted or overlooked by the research community. In this paper, an AAL-based smart cane system with security and privacy features for blind and visually impaired individuals that aims at satisfying these requirements is proposed. Multiple services that facilitate the everyday life for both indoor and outdoor activities are implemented: obstacle detection for ground and head level via ultrasonic (US) sensors and vibrations, ascending and descending stair detection/recognition via computer vision, image processing through various sensors, an emergency button for additional safety, and a LoRa antenna with a security and privacy mechanism for safely communicating with the Health 4.0-based environment. The proposed system is implemented with an Arduino and Raspberry Pi Zero combination and provides more practical and economic services compared to other published related works, including head-level detection, an indoor-outdoor adjustment switch and security mechanisms that are in most cases dismissed. It achieves a 7.4 % accuracy increase for general obstacle detection and a 100 % consistent drop or wall detection accuracy compared to published works. The proposed system presents a 37.82 % increase of speed-adjusted recall and a 24.4 % performance increase in its stair detection feature compared to published works. It focuses on hardware efficiency, safety and real-world autonomy with cost efficient alternatives. The proposed architecture of the security mechanism achieves a small area consumption, minimum of 35.6 % decrease compared to published designs, and an efficient throughput, that is appropriate with the utilized antenna.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"114 ","pages":"Article 105155"},"PeriodicalIF":1.9,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143906800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel machine learning-driven optimization methodology for faster and more efficient design space exploration in high-level synthesis","authors":"Esra Celik,&nbsp;Deniz Dal","doi":"10.1016/j.micpro.2025.105154","DOIUrl":"10.1016/j.micpro.2025.105154","url":null,"abstract":"<div><div>The optimization of digital circuits is a critical factor in determining the competitiveness of modern electronic systems, particularly in terms of area, performance, and power consumption. High-Level Synthesis (HLS) plays a pivotal role in this optimization process, enabling designers to define system requirements at a higher level of abstraction and providing opportunities to analyze and optimize digital circuits against various metrics prior to production. However, the design constraints inherent in the HLS process often lead to multi-objective optimization problems, which significantly complicate the exploration process. This complexity necessitates the development of novel synthesis methodologies enabling faster and more efficient design space exploration. In response to this need, within the scope of this study, we introduced an innovative and hybrid HLS methodology that combines metaheuristic and machine learning approaches. In this respect, two distinct synthesis tools were developed. The first tool, implemented in C++, utilizes the Simulated Annealing (SA) metaheuristic with a novel three-part solution representation. This representation, a key contribution of our study, aims to minimize the weighted sum of latency and area constraints for Data Flow Graph (DFG) designs. While effective, this approach resulted in extended execution times due to computationally intensive design variables. To address the performance bottleneck identified in the standard cost function evaluation, we developed a second tool that integrates machine learning with the traditional SA. This hybrid approach combines C++ and Python, incorporating a Support Vector Regression (SVR) model to estimate solution costs more efficiently, significantly reducing execution times. Our study also presents the detailed analyses of the experimental results conducted on seven benchmarks with varying node counts. The three-part solution representation in the traditional SA approach demonstrated up to a 53.38% improvement in performance compared to the single-part representation across all benchmarks. For benchmarks with fewer nodes (DiffEq, Lattice, Ellip, and FEWF), the model-based estimation implementation achieved results identical to the traditional approach but required longer execution times. For benchmarks characterized by higher node counts (MatMul, IntAux, and MCM), our novel approach demonstrated equivalent results to the traditional SA implementation with a time savings of up to 129 seconds. We leveraged these time savings to enhance the exploration process, achieving up to 5.4% improvement in solution quality without exceeding the execution time of the traditional approach.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"114 ","pages":"Article 105154"},"PeriodicalIF":1.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143881824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review on hardware accelerators for convolutional neural network-based inference engines: Strategies for performance and energy-efficiency enhancement","authors":"Deepika S․ ,&nbsp;Arunachalam V․ ,&nbsp;Alex Noel Joseph Raj","doi":"10.1016/j.micpro.2025.105146","DOIUrl":"10.1016/j.micpro.2025.105146","url":null,"abstract":"<div><div>In time-critical &amp; safety-critical image classification applications, Convolutional Neural Networks (CNNs) based Inference Engines (IEs) are preferred and required to be fast, accurate, and cost-effective to meet the market demands. The self-feature extraction capabilities use millions of parameters and neurons in the stack of layers with restricted processing time. This paper reviews strategies applied in Hardware-based image classification CNN inference engines. The acceleration strategies are (1) Arithmetic Logic Unit (ALU)-based, (2) Data flow-based, and (3) Sparsity-based are considered here. Considering benchmark accuracy, the 16-bit mixed fixed/floating point could provide 99 % and 3.75 times more performance than Half-precision floating point in an application-specific CNN model. Feeding 2-dimensional or 3-dimensional data frames to the CNN layers would reuse the data. It optimizes the volume of memory usage and improves the efficiency of the processor array. The pruning of zero/near-zero valued Input Feature Maps (IFMs) and weights leads to sparsity in the data fed to the different layers. Therefore, data compression strategies and skipping the trivial computation (zero skipping approach) would reduce the complexity of the controller. There is a benchmark performance improvement of 1.17 times and 6.2 times in power efficiency compared to dense architecture. Minimizing the complexity of indexing and load balancing controller would improve the performance further.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105146"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143510725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A cost-effective design for a mid-range microcontroller-based lock-in amplifier","authors":"Ignacio Horcas ,&nbsp;David Moreno-Salinas ,&nbsp;José Sánchez-Moreno","doi":"10.1016/j.micpro.2025.105145","DOIUrl":"10.1016/j.micpro.2025.105145","url":null,"abstract":"<div><div>Lock-in amplifiers are instruments widely used in physics and engineering laboratories, whose invention goes back to the 1940s. Due to the late electronic developments, the former analog implementations have been replaced with digital versions, mainly based on FPGAs (field-programmable gate arrays). The present work, exploiting the last advances in the microcontrollers field, consists in the development of a functional prototype of a low-cost lock-in amplifier based on a microcontroller with similar specifications to mid-range commercial amplifiers. The performance of the prototype has been tested and compared with commercial devices, showing a similar performance in common use cases at a much reduced cost.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105145"},"PeriodicalIF":1.9,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143453911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}