A reconfigurable PUF and TRNG design based on multiplexers for securing IoT applications

Abstract

Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) are two important hardware security primitives in modern cryptography. A regular arbiter PUF can be broken by machine learning (ML) attacks without much effort since a high linear relationship exists between the input data and the output response of the PUF. In this paper, an ML-resistant reconfigurable PUF and TRNG (RePT) architecture is proposed for the first time. Within this RePT design, a non-linearization technique by masking the linear relationship between the input data and the output response is proposed to greatly reinforce the robustness of an arbiter PUF against ML attacks without significantly increasing its area and power overhead. So as to further reuse the existing hardware resource within the arbiter PUF to build another hardware security primitive: TRNG, a novel algorithm is proposed to efficiently determine the selection signal value of each multiplexer within the arbiter PUF. As shown in the result, the proposed RePT design is able to achieve a 38 Mbps PUF (260 Mbps TRNG) throughput with 32,621 $\mu$m${}^2$ area, under the synthesis of SMIC 55 nm process design kits (PDK). Additionally, when ML attacks are performed on the proposed RePT circuit, it cannot be cracked even if 100,000 training data are enabled.