Microprocessors and Microsystems最新文献_第10页

Experimental evaluation of RISC-V micro-architecture against fault injection attack 针对故障注入攻击的 RISC-V 微体系结构实验评估

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-12-20 DOI: 10.1016/j.micpro.2023.104991

Maryam Esmaeilian, Hakem Beitollahi

{"title":"Experimental evaluation of RISC-V micro-architecture against fault injection attack","authors":"Maryam Esmaeilian, Hakem Beitollahi","doi":"10.1016/j.micpro.2023.104991","DOIUrl":"10.1016/j.micpro.2023.104991","url":null,"abstract":"<div><p><span>Today, the use of embedded processors is increasing dramatically and they are used in all aspects from our daily life to security applications. Physical access to hardware has made the hardware security a major concern. Hardware attacks compromise the hardware security by physically accessing target devices. Among the available techniques for hardware attacks, Fault Injection<span> Attacks (FIAs), such as clock glitching, are one of the most harmful types of non-invasive attacks that can disrupt the operation of an embedded system. Thus, it will be important and fundamental to evaluate </span></span>embedded software<span> programs before using them in critical applications and check their vulnerability against fault injection attacks. However, it is often difficult for software developers to assess vulnerabilities. In this paper, an easy-to-use platform is presented to facilitate the process of evaluating the vulnerability of programs running on embedded processors against clock glitching attacks. Our experimental results show the vulnerability window of RISC-V micro-architecture for different high-level C-functions. The results of this research can help the developers of embedded systems that are used in security applications to evaluate their system against clock glitching attacks with the least cost in a short time.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104991"},"PeriodicalIF":2.6,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139026463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved DWT and IDWT architectures for image compression 用于图像压缩的改进型 DWT 和 IDWT 架构

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-12-19 DOI: 10.1016/j.micpro.2023.104990

Ritesh Sur Chowdhury, Jhilam Jana, Sayan Tripathi, Jaydeb Bhaumik

{"title":"Improved DWT and IDWT architectures for image compression","authors":"Ritesh Sur Chowdhury, Jhilam Jana, Sayan Tripathi, Jaydeb Bhaumik","doi":"10.1016/j.micpro.2023.104990","DOIUrl":"10.1016/j.micpro.2023.104990","url":null,"abstract":"<div><p><span><span>In the recent era, a rapid development in the field of image processing<span> has been observed. One of the important applications in image processing is compression. Several wavelet transform based </span></span>image compression<span><span> techniques have already been introduced. In this paper, Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) based improved image compression and decompression techniques have been proposed by incorporating a scaling factor. The DWT and IDWT algorithms are implemented using folded architecture. To reduce the usages of hardware resources, a multiplier is recursively used. Image compression and decompression schemes based on proposed DWT and IDWT architectures are tested using four different image databases. The proposed technique provides better results in terms of bits per pixel, compression ratio, </span>mean square error, peak-signal-to-noise ratio, normalized correlation coefficient and structural similarity index. </span></span>FPGA<span> based synthesis has been performed using Xilinx Vivado Synthesis tool in terms of slice LUTs, slice registers, clock frequency, delay and power. The synthesis results show that proposed DWT and IDWT architectures are amenable for image compression and decompression applications.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104990"},"PeriodicalIF":2.6,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138820588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms 高效实施三维蜂窝遗传算法的新型分区策略

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-12-09 DOI: 10.1016/j.micpro.2023.104986

Martín Letras , Alicia Morales-Reyes , René Cumplido , María-Guadalupe Martínez-Peñaloza , Claudia Feregrino-Uribe

{"title":"A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms","authors":"Martín Letras , Alicia Morales-Reyes , René Cumplido , María-Guadalupe Martínez-Peñaloza , Claudia Feregrino-Uribe","doi":"10.1016/j.micpro.2023.104986","DOIUrl":"10.1016/j.micpro.2023.104986","url":null,"abstract":"<div><p><span><span><span>Solving optimization problems while fulfilling real-time constraints requires high algorithmic and processing performance. Cellular </span>Genetic Algorithms (cGAs) have been competitive at difficult single objective combinatorial and continuous domain problems. Moreover, it has been demonstrated that structural properties in cGAs, such as population topology dimension, local neighborhood configuration and ad-hoc selection mechanisms, allow not only further algorithmic improvement but also, these characteristics can be combined at hardware level for acceleration. In this article, a novel partition strategy to exploit 3D cGAs population dynamics on a 2D processing array using </span>Field Programmable Gate Arrays<span> (FPGAs) as the target processing platform is presented. The proposed architecture fits as an optimization module within an embedded system where real-time constraints must be fulfilled. Therefore, it is important to find an optimal trade-off between hardware resources usage and searching time. Overall results demonstrate that the proposed architecture can run up to 90 MHz when tackling continuous </span></span>benchmark functions<span>. Moreover, speed-up of up to three and two orders of magnitude are achieved in comparison to a single CPU and a parallel GPU respectively.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104986"},"PeriodicalIF":2.6,"publicationDate":"2023-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138610571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Retraction notice to “FPGA implementation of PMSG based AC conversion using soft switching twin–mode PWM/FPGA control for high power IM application” [Microprocessors and Microsystems 75 (2020) 103044] 关于“基于软开关双模PWM/FPGA控制的高功率IM应用中基于PMSG的交流转换的FPGA实现”的撤回通知[微处理器与微系统]75 (2020)103044]

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-30 DOI: 10.1016/j.micpro.2023.104977

C. Kadhiravan, J. Baskaran

引用次数: 0

Wiretap resisting and privacy preserving data exchange with physical layer security and blockchain based authentication in Internet of Vehicles 基于物理层安全和区块链认证的车联网防窃听、保隐私数据交换

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-23 DOI: 10.1016/j.micpro.2023.104965

Qiao Liu , Qi Han , Guangze Luo , Jin Cao , Hui Li , Yong Wang

{"title":"Wiretap resisting and privacy preserving data exchange with physical layer security and blockchain based authentication in Internet of Vehicles","authors":"Qiao Liu , Qi Han , Guangze Luo , Jin Cao , Hui Li , Yong Wang","doi":"10.1016/j.micpro.2023.104965","DOIUrl":"10.1016/j.micpro.2023.104965","url":null,"abstract":"<div><p>With the development of automobile industry technology, vehicles have greatly affected everyday life, work and other aspects. With the continuous innovation of sensor technology, computer technology, wireless communication<span><span><span> technology, and GPS technology, the concept of Inter of Vehicles (IoV) has been widely regarded as the core technology to solve a series of problems. However, as a complexity network with multiple elements including people, vehicle, base-station and so on, IoV is confronted with security threatened. In this paper, secure data exchange has been considered for two authenticated On Board Units (OBUs) with help of Road Side Unit (RSU). Blockchain based </span>authentication<span> and physical layer security have been applied into IoV for wiretap resisting and privacy preserving data exchange. For wiretap resisting, two synchronized transmitted signals from OBUs act as artificial noise at eavesdropper. In addition, for privacy preserving, summed codeword is formed at RSU which cannot be recovered individually. Finally, simulation results have been conducted to demonstrate that the proposed protocol can achieve transmission efficiency as well as </span></span>informatics security.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104965"},"PeriodicalIF":2.6,"publicationDate":"2023-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138515506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On the interactions between ILP and TLP with hardware transactional memory ILP和TLP与硬件事务性内存之间的相互作用

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-19 DOI: 10.1016/j.micpro.2023.104975

Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio

{"title":"On the interactions between ILP and TLP with hardware transactional memory","authors":"Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio","doi":"10.1016/j.micpro.2023.104975","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.104975","url":null,"abstract":"<div><p>Hardware implementations of Transactional Memory (HTM) are designed to facilitate efficient thread synchronization in parallel programs, encouraging the use of larger critical sections. By employing optimistic concurrency control to execute transactions speculatively, HTM systems promise to deliver the performance benefits typically associated with fine-grained locks. In doing so, HTM systems must deal with transaction aborts. While under certain conditions aborts may be caused by the inherent limitations of hardware structures employed to implement TM (e.g., caches), conflicting concurrent accesses to shared memory locations are generally the prevailing cause for squashing the work done by a transaction</p><p>In this study, we present what we believe to be, to the best of our knowledge, the first characterization of how the aggressiveness of processor cores, particularly their ability to exploit instruction-level parallelism (ILP), interacts with the support for optimistic thread-level speculation offered by HTM systems. We have observed that by adjusting the size of structures that facilitate out-of-order and speculative execution, the number of aborts in the execution of transactional workloads can be altered in best-effort HTM implementations. Our findings indicate that in scenarios with high contention, a smaller number of powerful cores is more suitable, whereas in low contention scenarios, using a larger number of less aggressive cores is preferable. In addition, HTM systems that employ lazy detection and those employing eager detection with requester-stalls resolution, benefit from using simpler cores. In conclusion, abort ratios can be reduced with a careful choice of both processor aggressiveness and design aspects for each application depending on its contention.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104975"},"PeriodicalIF":2.6,"publicationDate":"2023-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S014193312300220X/pdfft?md5=ce105b99f7f43d90376360a92db4669c&pid=1-s2.0-S014193312300220X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138404142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fault modeling for external energy or internal cell defect in quantum dot cellular automata 量子点元胞自动机中外部能量或内部细胞缺陷的故障建模

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-01 DOI: 10.1016/j.micpro.2023.104948

Debajyoty Banik

{"title":"Fault modeling for external energy or internal cell defect in quantum dot cellular automata","authors":"Debajyoty Banik","doi":"10.1016/j.micpro.2023.104948","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.104948","url":null,"abstract":"<div><p>Nanotechnology has made the circuits more susceptible to errors. It takes a lot of space and power to make sequential reversible circuits testable using one of the conventional methods (such as cascading gates with the original circuit). I suggest a superior testing strategy for sequential circuits based on conservative logic. The primary goal of this effort is to create a testable sequential circuit that is compact in terms of circuit area and other cost parameters. My method does not require changing the original circuit. So, incorporating testable features using the proposed method does not affect the complexity of the overall circuit. In this work, stuck-at-fault modeling for external unwanted energy or internal cell defect in low-power molecular QCA is also derived. The reversible double-edge triggered (DET) flip-flop is tested using the suggested approach. The proposed methodology can still be applied to achieve 100% fault coverage for unidirectional stuck-at-fault in quantum cellular automata (QCA) designs. The design is assigned into practice using a layered technique since it is more reliable and economical.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"103 ","pages":"Article 104948"},"PeriodicalIF":2.6,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92046144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Retraction notice to “Applications of internet of things (IOT) to improve the stability of a grid connected power system using interline power flow controller” [Microprocessors and Microsystems 76 (2020) 103038] 关于“物联网(IOT)在利用线间潮流控制器提高并网电力系统稳定性中的应用”的撤回通知[微处理器与微系统76 (2020)103038]

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-01 DOI: 10.1016/j.micpro.2023.104941

G. Radhakrishnan , V. Gopalakrishnan

引用次数: 0

Retraction notice to the articles published in the special issue embedded system from “Microprocessors and Microsystems” 《微处理器与微系统》嵌入式系统专刊文章撤回通知

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-01 DOI: 10.1016/j.micpro.2023.104972

引用次数: 0

Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis 在高级合成过程中探索最优功能抗特洛伊木马硬件知识产权(IP)核心设计

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2023-11-01 DOI: 10.1016/j.micpro.2023.104973

Anirban Sengupta, Aditya Anshul, Rahul Chaurasia

{"title":"Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis","authors":"Anirban Sengupta, Aditya Anshul, Rahul Chaurasia","doi":"10.1016/j.micpro.2023.104973","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.104973","url":null,"abstract":"<div><p>Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial. This paper presents a novel exploration of optimal hardware IP core design methodology with Trojan defense capability (<em>i.e.,</em> detection and isolation) during high level synthesis (HLS) that provides isolation of functional Trojan in a system design to ensure reliable and correct functional behavior. The proposed methodology is robust and provides the capability to yield the correct output value using HLS-based triple modular redundancy (TMR) logic and a distinct multivendor allocation policy. Therefore, the proposed HLS methodology can generate an optimal hardware IP core/system-on-chip (SoC) design with functional Trojan defense capability. The paper presents an overall flow of the proposed methodology along with a demonstrative case study on designing optimal Trojan resistant finite impulse response filter (FIR) hardware SoC design. Results of the proposed approach are evaluated in terms of design cost, convergence time, security and optimality analysis, and comparison with prior works. The proposed approach is able to generate fully functional Trojan-resistant optimal SoC designs with minimum overhead, as evident from optimality analysis and design cost.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"103 ","pages":"Article 104973"},"PeriodicalIF":2.6,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134656190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0