High throughput DLP and mixed radix based architectures of Viterbi decoder

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mohamed Asan Basiri M.
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引用次数: 0

Abstract

Viterbi decoders play an important role in digital communication. This manuscript proposes two high throughput VLSI architectures of Viterbi decoder. In the first proposed architecture, the data level parallelism (DLP) based Viterbi decoder of rate 1N can be used to perform 1, 2, 4, 8, …parallel decodings of rates 1N, 1(N/2), 1(N/4), 1(N/8), …respectively. The second proposed mixed radix Viterbi decoder architecture is to perform four numbers of radix-2k1 decodings in parallel using one radix-2k Viterbi decoder, where k1. All the conventional and proposed Viterbi decoders are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the proposed designs achieve high throughput as compared with the conventional designs. According to the synthesis results, the proposed mixed radix-2&4 decoder achieves 73.9% of improvement in maximum throughput as compared with the conventional radix-4 design.
高吞吐量DLP和基于混合基数的维特比解码器架构
维特比解码器在数字通信中起着重要的作用。本文提出了两种高吞吐量Viterbi译码器的VLSI架构。在第一种结构中,基于数据级并行(DLP)的1N速率的Viterbi解码器可以分别进行速率为1N、1(N/2)、1(N/4)、1(N/8)、…的1、2、4、8、…的并行解码。第二种提出的混合基数Viterbi解码器架构是使用一个基数2k的Viterbi解码器并行执行四个数的基数2k−1解码,其中k≥1。所有传统的和提出的维特比解码器都是使用Cadence在45纳米CMOS技术上实现的。综合结果表明,与传统设计相比,所提出的设计具有较高的通量。综合结果表明,所提出的混合radix-2&;4解码器与传统的radix-4设计相比,最大吞吐量提高了73.9%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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