High throughput DLP and mixed radix based architectures of Viterbi decoder

Viterbi decoders play an important role in digital communication. This manuscript proposes two high throughput VLSI architectures of Viterbi decoder. In the first proposed architecture, the data level parallelism (DLP) based Viterbi decoder of rate $\frac{1}{N}$ can be used to perform 1, 2, 4, 8, …parallel decodings of rates $\frac{1}{N}$, $\frac{1}{(N/2)}$, $\frac{1}{(N/4)}$, $\frac{1}{(N/8)}$, …respectively. The second proposed mixed radix Viterbi decoder architecture is to perform four numbers of radix-$2^{k-1}$ decodings in parallel using one radix-$2^k$ Viterbi decoder, where $k\ge 1$. All the conventional and proposed Viterbi decoders are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the proposed designs achieve high throughput as compared with the conventional designs. According to the synthesis results, the proposed mixed radix-2&4 decoder achieves 73.9% of improvement in maximum throughput as compared with the conventional radix-4 design.