Improving performance of simultaneous multithreading CPUs using autonomous control of speculative traces

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems Pub Date : 2024-05-26 DOI:10.1016/j.micpro.2024.105073

Ryan F. Ortiz, Wei-Ming Lin

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引用次数: 0

Abstract

Simultaneous Multithreading (SMT) allows for a processor to concurrently execute multiple independent threads while sharing certain data path components to optimize resource waste. Speculative execution allows for these processors to take advantage of Instruction-Level Parallelism but the penalty for a miss speculation includes the wasting of resources amongst these shared resources where clock cycles are wasted at a time. In this paper we show that an average of 13 % of instructions are flushed as a result of incorrect predictions. These flushed out instructions could have potentially taken up shared resources which other non-speculative threads could have used. This paper proposes a technique that can dynamically adjust how many speculative instructions a thread can rename and decode aiming to diminish the waste of the shared resources. Our simulation results show, with the proposed technique, that the average flushed out instruction rate is reduced by 23 % and average throughput is improved by 13 %.

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利用投机跟踪的自主控制提高同步多线程 CPU 的性能

同时多线程（SMT）允许处理器同时执行多个独立线程，同时共享某些数据路径组件，以优化资源浪费。投机执行允许这些处理器利用指令级并行性，但投机失误的惩罚包括在这些共享资源中浪费资源，每次都会浪费时钟周期。本文显示，由于预测错误，平均有 13% 的指令被刷新。这些被刷新的指令可能占用了其他非推测线程本可以使用的共享资源。本文提出了一种可动态调整线程重命名和解码投机指令数量的技术，旨在减少对共享资源的浪费。我们的仿真结果表明，采用该技术后，平均刷新指令率降低了 23%，平均吞吐量提高了 13%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microprocessors and Microsystems 工程技术-工程：电子与电气

CiteScore

6.90

自引率

3.80%

发文量

204

审稿时长

172 days

期刊介绍： Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.