发布求助
文献互助 智能选刊 最新文献

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.最新文献

筛选
英文 中文
Advanced module packaging method 先进的模块封装方法
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194735
P. Salmon
{"title":"Advanced module packaging method","authors":"P. Salmon","doi":"10.1109/ISQED.2003.1194735","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194735","url":null,"abstract":"An intermediate solution between conventional printed circuit board technology and wafer level packaging, WLP, is to fabricate interconnection circuits and flip chip assembly structures on large glass substrates using LCD manufacturing equipment. Trace widths of 5 microns and a trace pitch of 10 microns are achievable on flexible substrates as large as 1800/spl times/1500 mm. Back planes for displays and keyboards can also utilize thin film transistors, TFTs, as developed for LCDs and enhanced for flexible assemblies (200/spl deg/C processing). A flexible circuit is built on a glass carrier with an intermediate release layer. The carrier is discarded after all processing is complete, including interconnection circuits, IC chip assembly, test and rework. The assembly method uses gold stud bumps on IC chips, and corresponding wells filled with solder on the motherboard 100-micron pad pitch is achievable for IC chips, module cables, and test connections. Avoidance of epoxy under layers contributes to a robust capability for reworking defective IC chips. The methods are applicable to a wide range of products, from cell phones to blade servers.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132864136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of interconnect pattern density information on a 90 nm technology ASIC design flow 互连模式密度信息对90nm工艺ASIC设计流程的影响
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194767
P. Zarkesh-Ha, S. Lakshminarayann, K. Doniger, W. Loh, P. Wright
{"title":"Impact of interconnect pattern density information on a 90 nm technology ASIC design flow","authors":"P. Zarkesh-Ha, S. Lakshminarayann, K. Doniger, W. Loh, P. Wright","doi":"10.1109/ISQED.2003.1194767","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194767","url":null,"abstract":"The importance of an interconnect pattern density model in ASIC design flow for a 90 nm technology is presented. It is shown that performing the timing analysis at the worst-case corner model for interconnect variation, without the knowledge of interconnect pattern density, often results in overdesign. Our experiments on real ASIC products indicate that knowledge of interconnect pattern density in timing analysis of 90 nm ASIC design flow prevents such overdesign. Quantitatively, it is shown that considering only the worst-case corner model in a global net results in a 10% delay overdesign. To meet the target delay for the net, it is sufficient to use a 45% smaller gate, which results in a 32% reduction in gate power dissipation, as well. It is, therefore, imperative to take into account the interconnect pattern density information in ASIC design flow of 90 nm and future technologies.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Generation of hazard identification functions 生成危害识别功能
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194769
M. Michael, S. Tragoudas
{"title":"Generation of hazard identification functions","authors":"M. Michael, S. Tragoudas","doi":"10.1109/ISQED.2003.1194769","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194769","url":null,"abstract":"We study the problem of identifying the complete set of pairs of input patterns that can cause different types of hazards to appear at a circuit line. A novel methodology to implicitly identify all possible input configurations is proposed. The technique is based on a systematic derivation of the conditions for the occurrence of static and dynamic hazards at a line, which are subsequently formulated as Boolean functions defined over variables representing the primary input signals. Our experimental results demonstrate that the proposed approach is very promising and outperforms existing approaches. In addition, they show that a proposed solution for the decision problem of hazard existence at a circuit line is very efficient.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116741509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design techniques for gate-leakage reduction in CMOS circuits 减少CMOS电路栅漏的设计技术
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194710
R. Guindi, F. Najm
{"title":"Design techniques for gate-leakage reduction in CMOS circuits","authors":"R. Guindi, F. Najm","doi":"10.1109/ISQED.2003.1194710","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194710","url":null,"abstract":"Oxide tunneling current in MOS transistors is fast becoming a non-negligible component of power consumption, as gate oxides get thinner, and could become in the future the dominant leakage mechanism in sub-100 nm CMOS circuits. In this paper, we present an analysis of static CMOS circuits from a gate-leakage point of view. We first consider the dependence of the gate current on various conditions for a single transistor and identify 3 main regions in which a MOS transistor will operate between clock transitions. The amount of gate-current differs by several orders of magnitude from one region to another. Whether a transistor will leak significantly or not is determined by its position in relation to other transistors within a structure. By comparing logically equivalent but structurally different CMOS circuits, we find that the gate current exhibits a 'structure dependence'. Also, the total gate-leakage in a given structure varies significantly for different combinations of inputs, from which we derive \"state-dependent gate-leakage tables\" that can be used to estimate the total amount of gate-current for a large circuit. Finally, we suggest guidelines aimed at reducing the amount of oxide-leakage current based on the presented structure and state dependencies.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Reliability evaluation for integrated circuit with defective interconnect under electromigration 电迁移下互连缺陷集成电路可靠性评估
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194705
Xiangdong Xuan, A. Singh, A. Chatterjee
{"title":"Reliability evaluation for integrated circuit with defective interconnect under electromigration","authors":"Xiangdong Xuan, A. Singh, A. Chatterjee","doi":"10.1109/ISQED.2003.1194705","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194705","url":null,"abstract":"In electromigration degradation process the existing physical defects on interconnect play a critical role by significantly accelerating the EM damage under increased current density and elevated temperature. In this work the simulation models were upgraded in the IC reliability simulator ARET to incorporate the effect of interconnect physical defects in expected lifetime prediction. Then based on the statistical approach, a probability model was developed to evaluate the system-level circuit reliability with defective interconnect under EM degradation. The probability model has been successfully implemented in ARET tool to simulate and evaluate both interconnect and circuit level reliabilities.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128968390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Concurrent fault detection in random combinational logic 随机组合逻辑中的并发故障检测
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194770
P. Drineas, Y. Makris
{"title":"Concurrent fault detection in random combinational logic","authors":"P. Drineas, Y. Makris","doi":"10.1109/ISQED.2003.1194770","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194770","url":null,"abstract":"We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor that immediately detects potential faults by comparison to the original circuit. However, instead of duplicating the circuit, the proposed method selects a small number of prediction logic functions which only partially replicate it. Selection is guided by the objective of minimizing the incurred hardware overhead at the cost of introducing fault detection latency. To achieve this, the proposed method replicates only a reduced width output function for every input combination, yet without compromising the ability to detect all faults. In contrast to concurrent error detection schemes which presume the ability to re-synthesize the circuit, the proposed method does not interfere with the implementation of the original design. As compared to previous approaches, the proposed method achieves significant hardware overhead reduction, while detecting all faults with very low average fault detection latency.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"23 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123330950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling 金属填充引起的电容偏差及有效互连几何建模研究
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194761
Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, J. Kong
{"title":"Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling","authors":"Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, J. Kong","doi":"10.1109/ISQED.2003.1194761","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194761","url":null,"abstract":"In this paper, the influence of floating dummy metal-fills on interconnect parasitic is analyzed with the variations of possible factors which can affect the capacitance. Recently proposed chip-level metal-fill modeling, replacing metal-fill layer with effective high-k dielectric, has been reviewed in detail. Using a systematized modeling flow, the property of the effective permittivity in the modeled geometry is examined. Validation with the realistic 3D structures clearly demonstrates the importance and correctness of the geometry modeling.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124034946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Monolithic DC-DC converter analysis and MOSFET gate voltage optimization 单片DC-DC变换器分析及MOSFET栅极电压优化
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194746
V. Kursun, S. Narendra, V. De, E. Friedman
{"title":"Monolithic DC-DC converter analysis and MOSFET gate voltage optimization","authors":"V. Kursun, S. Narendra, V. De, E. Friedman","doi":"10.1109/ISQED.2003.1194746","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194746","url":null,"abstract":"The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 /spl mu/m CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124111350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Analysis of IR-drop scaling with implications for deep submicron P/G network designs 深亚微米P/G网络设计中红外降标度分析
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194706
A. Ajami, K. Banerjee, A. Mehrotra, Massoud Pedram
{"title":"Analysis of IR-drop scaling with implications for deep submicron P/G network designs","authors":"A. Ajami, K. Banerjee, A. Mehrotra, Massoud Pedram","doi":"10.1109/ISQED.2003.1194706","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194706","url":null,"abstract":"This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114763210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
Revisiting the noise figure design metric for digital communication receiver 再论数字通信接收机噪声系数设计指标
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194725
W. Namgoong, J. Lerdworatawee
{"title":"Revisiting the noise figure design metric for digital communication receiver","authors":"W. Namgoong, J. Lerdworatawee","doi":"10.1109/ISQED.2003.1194725","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194725","url":null,"abstract":"Noise figure is a commonly used system parameter that quantifies the degradation in the signal-to-noise ratio (SNR) as the signal passes through a receiving system. Because of the difficulty in defining the SNR, NF depends on how the SNR is computed and the underlying assumptions that are made. Existing NF measures and their shortcomings are explained. A new NF suitable for digital communication receiver is proposed by redefining the SNR, so that the NF measures the degradation in the achievable performance caused by the receiving system. The proposed NF, which we refer to as the effective NF, can be readily determined based on the existing NF measurement techniques.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128475857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信