Impact of interconnect pattern density information on a 90 nm technology ASIC design flow

Abstract

The importance of an interconnect pattern density model in ASIC design flow for a 90 nm technology is presented. It is shown that performing the timing analysis at the worst-case corner model for interconnect variation, without the knowledge of interconnect pattern density, often results in overdesign. Our experiments on real ASIC products indicate that knowledge of interconnect pattern density in timing analysis of 90 nm ASIC design flow prevents such overdesign. Quantitatively, it is shown that considering only the worst-case corner model in a global net results in a 10% delay overdesign. To meet the target delay for the net, it is sufficient to use a 45% smaller gate, which results in a 32% reduction in gate power dissipation, as well. It is, therefore, imperative to take into account the interconnect pattern density information in ASIC design flow of 90 nm and future technologies.