Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.最新文献

Electrical and thermal analysis for system-in-a package (SiP) implementation platform 系统级封装(SiP)实现平台的电气和热分析

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194736

Michael X. Wang, Katsuharu Suzuki, W. Dai

引用次数: 3

Noise-aware driver modeling for nanometer technology 纳米技术的噪声感知驱动建模

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194728

Xiaoliang Bai, R. Chandra, S. Dey, P. V. Srinivas

{"title":"Noise-aware driver modeling for nanometer technology","authors":"Xiaoliang Bai, R. Chandra, S. Dey, P. V. Srinivas","doi":"10.1109/ISQED.2003.1194728","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194728","url":null,"abstract":"With the semiconductor industry evolving into the deep sub-micron (DSM) era, crosstalk noise becomes a critical issue that needs to be handled efficiently and accurately. Modern designs like system-on-chips have millions of noise-prone wires that need to be analyzed. Analysis using circuit-level simulation is not feasible. Efficient static noise analysis, which statically estimate noise based on linear circuit model, is widely used. However, traditionally drivers' holding resistances are pre-characterized without considering the crosstalk noise. The driver's holding resistance changes dramatically with the crosstalk noise induced voltage changing on the victim wire. For accurate noise estimation, the driver's substantial nonlinear variation cannot be ignored. In this paper, we propose a novel method, which uses layout extracted parameters of coupling interconnect and pre-characterized parameters of driver to calculate an effective holding resistance. The noise-aware effective holding resistance dramatically improves the accuracy for noise magnitude and energy estimation. The proposed method is simple and efficient. It enables fast on-the-fly calculation of the effective holding resistance. Experiments show significant improvement in accuracy with almost negligible computation overhead.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"14 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116813241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Procedural analog design (PAD) tool 程序模拟设计(PAD)工具

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194751

D. Stefanovic, M. Kayal, M. Pastre, V. Litovski

引用次数: 14

Static pin mapping and SOC test scheduling for cores with multiple test sets 静态引脚映射和SOC测试调度与多个测试集的核心

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194716

Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, N. Mukherjee, S. Reddy

引用次数: 15

Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits 静电放电注入提高堆叠NMOS在混合I/O接口电路中的机模ESD稳健性

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194759

M. Ker, Hsin-Chyh Hsu, Jeng-Jie Peng

引用次数: 2

Leakage current reduction in sequential circuits by modifying the scan chains 通过修改扫描链减少顺序电路中的漏电流

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194708

A. Abdollahi, F. Fallah, Massoud Pedram

引用次数: 7

Parameterized macrocells with accurate delay models for core-based designs 基于核心设计的具有精确延迟模型的参数化宏单元

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194752

M. Mansour, Mohammad M. Mansour, A. Mehrotra

{"title":"Parameterized macrocells with accurate delay models for core-based designs","authors":"M. Mansour, Mohammad M. Mansour, A. Mehrotra","doi":"10.1109/ISQED.2003.1194752","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194752","url":null,"abstract":"In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC's). This methodology provides the flexibility for instance-based cores to be easily customized for application requirements. By using few scaling parameters to characterize a PMC, a macrocell can be instantiated in virtually any size depending on the required performance. Moreover a new first-order macro delay model is proposed which is a function of the scaling parameters of the PMC which enables accurate delay predictions at the subsystem/core level. The proposed delay model is suitable for use by a delay optimizer to determine the optimum scaling parameters of individual PMC's in a core. A PMC library has been developed and used to design cores for communications applications. To demonstrate the effectiveness of the proposed methodology, several subsystems used in a channel LDPC decoder were synthesized using this library where the individual PMC's were optimized for minimum delay. The resulting custom-quality layout have areas ranging from 40/spl times/100 /spl mu/m/sup 2/ to 380/spl times/200 /spl mu/m/sup 2/ and delay in the range of 1.6 ns to 10 ns in 0.18 /spl mu/m, 1.8 V CMOS technology.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"47 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134260773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Static electromigration analysis for signal interconnects 信号互连的静电迁移分析

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194762

C. Oh, D. Blaauw, M. Becer, V. Zolotov, R. Panda, A. Dasgupta

{"title":"Static electromigration analysis for signal interconnects","authors":"C. Oh, D. Blaauw, M. Becer, V. Zolotov, R. Panda, A. Dasgupta","doi":"10.1109/ISQED.2003.1194762","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194762","url":null,"abstract":"With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, RMS, and peak current values for each wire segment. However, this approach cannot be applied to large problem sizes where hundreds of thousands of nets must be analyzed, each consisting of many thousands of RC elements. In this paper, we propose a static electromigration analysis approach. We show that under conditions that are typically met by VLSI interconnects, the charge transfer through wire segments of a net can be calculated directly by solving a system of linear equations, thereby eliminating the need for time domain simulation. Also, we prove that under these conditions the charge transfer through a wire segment is independent of the shape of the driver current waveform. From the charge transfer through each wire segment, the average current is obtained directly, as well as approximate RMS and peak currents. We account for the different possible switching scenarios that give rise to unidirectional or bi-directional current by separating the charge transfer from the rising and falling transitions, and also propose approaches for modeling multiple simultaneous switching drivers. The results on a number of industrial circuits demonstrate the accuracy and efficiency of the approach.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134437051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay 用于分析电感对片上互连延迟影响的电感振荡器的设计与测量

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194765

Takashi Sato, H. Masuda

引用次数: 5

Analyzing statistical timing behavior of coupled interconnects using quadratic delay change characteristics 利用二次延迟变化特性分析耦合互连的统计时序行为

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194729

Tom Chen, A. Hajjar

引用次数: 4