Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.最新文献_第2页

Design considerations of scaled sub-0.1 /spl mu/m PD/SOI CMOS circuits 小于0.1 /spl mu/m的PD/SOI CMOS电路的设计考虑

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194724

C. Chuang, R. Joshi, R. Puri, Keunwoo Kim

引用次数: 2

LYS: a solution for system on chip (SoC) production cost and time to volume reduction LYS:片上系统(SoC)生产成本和减少批量时间的解决方案

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194714

Jean-Pierre Heliot, Florent Parmentier, M. Baron

{"title":"LYS: a solution for system on chip (SoC) production cost and time to volume reduction","authors":"Jean-Pierre Heliot, Florent Parmentier, M. Baron","doi":"10.1109/ISQED.2003.1194714","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194714","url":null,"abstract":"With the introduction of new generations of systems on chip (SoC) on 0.18 /spl mu/m and 0.12 /spl mu/m technologies, the production cost and time to volume become more and more critical, on top of best in class level of quality and reliability. The SoC approach-widely based on the usage of cell libraries or reusable IP blocks-brings extreme complexity. Accurate knowledge and level of validation on silicon of each block of library/IP used within new chip becomes mandatory in order to secure first silicon success. In this context, knowledge sharing between users of the same IP in different SoC plays a key role in cost optimisation and time to volume reduction. This paper describes the information system solution developed on 0.18 /spl mu/m technology, named LYS (Library Yield System). LYS allows keeping track of the version of library cells or reusable IP blocks used within each SoC of a given technology. Each SoC project is analysed at different steps of its life cycle starting from product specification up to silicon qualification. Block by block silicon results applied to SoC, and early warning system linking the different projects together, allow to optimise and update in real time the content of each projects, and to perform the needed improvements. This methodology allows, before mask order, any new project to be updated with appropriate library or IP blocks revision in order to get rid of known silicon issues detected on previous projects. This solution is now fully implemented and in use on 0.35 /spl mu/m, 0.25 /spl mu/m, 0.18 /spl mu/m, 0.12 /spl mu/m, and 90 nm technologies. As far as we know, there is no equivalent solution available and running in microelectronics companies.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116154075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Impact of interoperability on CAD-IP reuse: an academic viewpoint 互操作性对CAD-IP复用的影响:一个学术观点

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194733

A. Kahng, I. Markov

引用次数: 1

Coupled simulation of circuit and piezoelectric laminates 电路与压电层压板的耦合仿真

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194760

Chenggang Xu, T. Fiez, K. Mayaram

引用次数: 1

Solving the SoC test scheduling problem using network flow and reconfigurable wrappers 利用网络流和可重构包装器解决SoC测试调度问题

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194715

S. Koranne

引用次数: 6

Analyzing internal-switching induced simultaneous switching noise 分析内部开关引起的同步开关噪声

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194768

Li Yang, J. Yuan

引用次数: 10

On the accuracy of return path assumption for loop inductance extraction for 0.1 /spl mu/m technology and beyond 0.1 /spl mu/m及以上工艺回路电感提取回路假设的准确性

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194766

Soyoung Kim, Y. Massoud, S. Wong

引用次数: 43

Hidden quality, crouching customer - how much does the quality of EDA tools impact electronic design? 隐藏的质量，蜷缩的客户——EDA工具的质量对电子设计的影响有多大?

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194763

T. Maniwa

{"title":"Hidden quality, crouching customer - how much does the quality of EDA tools impact electronic design?","authors":"T. Maniwa","doi":"10.1109/ISQED.2003.1194763","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194763","url":null,"abstract":"Description In today’s fast-paced electronics market, design engineers face incredible challenges keeping up with increasingly complex technology and time-to-market pressures. Many design engineers facing these challenges say that quality problems with their EDA tools cost them dearly in lost productivity and in missed deadlines. At the same time, the same design engineers also say that they urgently need better technology, features, and special functions in the EDA tools they use in their work. Thus, Quality in EDA products is crucial to customer success or is it? How much quality is enough to keep the industry moving at its fast pace? Is quality a hidden dragon that could cause customers to crouch in fear? What are the costs and who will pay for higher quality? Can EDA customers have their cake and eat it too? Examples of some provocative questions that can be posed are: “For the user is EDA quality worth the hype at the expense of technology?” “Do mainstream and power users want higher quality or more functionality” “Do users of front-end and back-end tools require different level of quality?” This panel will examine the core issues of quality in EDA products and the impact on electronic design — from the viewpoints of customers, EDA vendors and independent analysts.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122900002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Using integer equations for high level formal verification property checking 使用整数方程进行高级形式验证属性检查

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194711

B. Alizadeh, M. R. Kakoee

引用次数: 14

Active device under bond pad to save I/O layout for high-pin-count SOC 键垫下的有源器件，可为高引脚数SOC节省I/O布局

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194738

M. Ker, Jeng-Jie Peng, H. Jiang

引用次数: 5