分析内部开关引起的同步开关噪声

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI:10.1109/ISQED.2003.1194768

Li Yang, J. Yuan

{"title":"分析内部开关引起的同步开关噪声","authors":"Li Yang, J. Yuan","doi":"10.1109/ISQED.2003.1194768","DOIUrl":null,"url":null,"abstract":"The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Analyzing internal-switching induced simultaneous switching noise\",\"authors\":\"Li Yang, J. Yuan\",\"doi\":\"10.1109/ISQED.2003.1194768\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.\",\"PeriodicalId\":448890,\"journal\":{\"name\":\"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-03-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2003.1194768\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2003.1194768","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

研究了内开关引起的同步开关噪声(SSN)。与驱动片外负载引起的地面反弹不同，电源轨和地轨线/引脚阻抗在评估内部SSN时都很重要，并且应该考虑双负反馈机制。在集总模型分析的基础上，考虑了MOS晶体管的寄生效应和速度饱和效应，建立了一个包含开关门和非开关门的分析模型。利用该模型对片上去耦电容、线脚电感效应和负载效应进行了解析分析。对亚微米工艺的模拟结果与SPICE模拟结果吻合较好。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Analyzing internal-switching induced simultaneous switching noise

The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

自引率

0.00%

发文量