LYS: a solution for system on chip (SoC) production cost and time to volume reduction

Abstract

With the introduction of new generations of systems on chip (SoC) on 0.18 /spl mu/m and 0.12 /spl mu/m technologies, the production cost and time to volume become more and more critical, on top of best in class level of quality and reliability. The SoC approach-widely based on the usage of cell libraries or reusable IP blocks-brings extreme complexity. Accurate knowledge and level of validation on silicon of each block of library/IP used within new chip becomes mandatory in order to secure first silicon success. In this context, knowledge sharing between users of the same IP in different SoC plays a key role in cost optimisation and time to volume reduction. This paper describes the information system solution developed on 0.18 /spl mu/m technology, named LYS (Library Yield System). LYS allows keeping track of the version of library cells or reusable IP blocks used within each SoC of a given technology. Each SoC project is analysed at different steps of its life cycle starting from product specification up to silicon qualification. Block by block silicon results applied to SoC, and early warning system linking the different projects together, allow to optimise and update in real time the content of each projects, and to perform the needed improvements. This methodology allows, before mask order, any new project to be updated with appropriate library or IP blocks revision in order to get rid of known silicon issues detected on previous projects. This solution is now fully implemented and in use on 0.35 /spl mu/m, 0.25 /spl mu/m, 0.18 /spl mu/m, 0.12 /spl mu/m, and 90 nm technologies. As far as we know, there is no equivalent solution available and running in microelectronics companies.