Design considerations of scaled sub-0.1 /spl mu/m PD/SOI CMOS circuits

Abstract

This paper reviews the circuit design considerations of scaled sub-0.1 /spl mu/m partially-depleted SOI (PD/SOI) CMOS circuits for high-performance digital applications. The impact of technology/device scaling and design challenges are highlighted. Unique design aspects and issues resulting from the scaling of PD/SOI device structure, such as parasitic bipolar effect and reduced-V/sub T/ leakage, hysteretic V/sub T/ variation, low-voltage impact ionization, higher V/sub T,lin/ to maintain adequate V/sub T,sat/, scaling/thinning of Si film, gate-to-body tunneling current, self-heating, soft error rate (SER), and the introduction of strained-Si channel on SOI are addressed.