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Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.最新文献

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Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis 利用全芯片串扰分析的函数关系消除假攻击者
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194756
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, J. Kong
{"title":"Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis","authors":"Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, J. Kong","doi":"10.1109/ISQED.2003.1194756","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194756","url":null,"abstract":"As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We propose a method to determine whether aggressors can potentially switch simultaneously with the victim or not. The functional information is used to classify the aggressors. Our functional pruning algorithm inspects the conflict of the net states using CNF (conjunction normal form) and BDD (binary decision diagram). We present the experimental results on several industrial circuits. In the experiments, 6.4% of total aggressors are false and the accuracy of delay calculation can be improved up to 36.6%.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122631213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Assessment of the OpenAccess Standard: insights on the new EDA industry standard from Hewlett-Packard, a Beta partner and contributing developer 开放存取标准的评估:来自Hewlett-Packard (Beta合作伙伴和贡献开发者)对新的EDA行业标准的见解
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194732
Terry Blanchard
{"title":"Assessment of the OpenAccess Standard: insights on the new EDA industry standard from Hewlett-Packard, a Beta partner and contributing developer","authors":"Terry Blanchard","doi":"10.1109/ISQED.2003.1194732","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194732","url":null,"abstract":"The rapidly increasing complexity and quality requirements of integrated circuit design can only be addressed effectively by a design system architecture that supports very efficient, high-quality sharing of IC design data. The OpenAccess Coalition is delivering an industry standard application programming interface (API) and information model (IM) that provides access to a shared database as an essential infrastructure component for modern IC design systems. The OpenAccess Standard IM and API, along with its reference implementation will be released to the industry early in 2003. Hewlett-Packard has participated in OpenAccess from the outset and most recently as a Beta evaluation partner for this OA industry release. HP has discovered many insights about the OpenAccess standardization process as well as specifically about the IM/API Standard and its reference implementation, which will be summarized herein, and explained in more detail during the presentation at the ISQED Conference.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127171321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quality soc design and implementation for real manufacturability 质量soc设计和实现真正的可制造性
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194703
S. Kohyama
{"title":"Quality soc design and implementation for real manufacturability","authors":"S. Kohyama","doi":"10.1109/ISQED.2003.1194703","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194703","url":null,"abstract":"Device miniaturization near 100nm node and beyond together with extreme multi-level interconnect started to create fundamental economical and engineering challenges. Especially, past success model of “Layer Masters” confessed difficulties to fill the gaps between each separated layers to complete integrated results, for meeting performance and yield with a reasonable timing. However, it is also obvious that classic IDM model proved to be so inefficient, since inevitable separation and standardization of various aspects of design and technology are not established adequately. Those issues are even more significant when we discuss complex SoC’s for 90nm and 65nm nodes, where design and implementation commingle in various different manners. A solution for these challenges is a new open IDM model where open collaboration and strong differentiator are essential. This presentation will discuss from a “SoC centric Open IDM” perspective, the whole flow of design and implementation for real manufacturability, where true knowledge of integration and management skill function to enhance differentiators on top of open platforms.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"16 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy 基于选择性基因治疗的遗传算法的电源噪声抑制时钟调度
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194753
Wai-Ching Douglas Lam, Cheng-Kok Koh, C. Tsao
{"title":"Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy","authors":"Wai-Ching Douglas Lam, Cheng-Kok Koh, C. Tsao","doi":"10.1109/ISQED.2003.1194753","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194753","url":null,"abstract":"Simultaneous switching events in the clock lines and almost simultaneous switching events of sequential and combinational logic elements cause large L/spl middot/di/dt and IR voltage variations in the power and ground network of a circuit. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose a genetic algorithm based clock scheduling approach for minimizing the number of simultaneous switching events such that the power supply noise is suppressed. We ensure that in any generation of the genetic algorithm process, there will be feasible clock schedules present in the gene pool by the use of gene therapy. Experimental results on benchmark circuits show an average reduction of 26.2% in the peak current, an average reduction of 37.9% in the current swing, and an average reduction of 46.2% in voltage variations in the power lines.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Active device under bond pad to save I/O layout for high-pin-count SOC 键垫下的有源器件，可为高引脚数SOC节省I/O布局
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194738
M. Ker, Jeng-Jie Peng, H. Jiang
{"title":"Active device under bond pad to save I/O layout for high-pin-count SOC","authors":"M. Ker, Jeng-Jie Peng, H. Jiang","doi":"10.1109/ISQED.2003.1194738","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194738","url":null,"abstract":"To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 /spl mu/m one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"62 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132360856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Using integer equations for high level formal verification property checking 使用整数方程进行高级形式验证属性检查
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194711
B. Alizadeh, M. R. Kakoee
{"title":"Using integer equations for high level formal verification property checking","authors":"B. Alizadeh, M. R. Kakoee","doi":"10.1109/ISQED.2003.1194711","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194711","url":null,"abstract":"This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verification methods use BDDs, as a low level representation of a design. BDD operations require separation of data and control parts of a design and their implementation requires large CPU time and memory. In our method; a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. This reduces the need for large BDD data structures and uses far less memory. Furthermore, this method is applied to circuits without having to separate their data and control sections. Integer equations are solved recursively by replacement and simplification operations. For this implementation, we use a canonical form of integer equations. This paper compares our results with those of the VIS verification tool that is a BDD based program.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134348761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Automatic repositioning technique for digital cell based window comparators and implementation within mixed-signal DfT schemes 基于数字单元的窗口比较器自动重定位技术及其在混合信号DfT方案中的实现
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194771
D. Venuto, M. Ohletz, B. Riccò
{"title":"Automatic repositioning technique for digital cell based window comparators and implementation within mixed-signal DfT schemes","authors":"D. Venuto, M. Ohletz, B. Riccò","doi":"10.1109/ISQED.2003.1194771","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194771","url":null,"abstract":"The possibility of using window comparators for the on-chip evaluation of signals in the analogue circuit part has been demonstrated and is shortly summarized. One of the problems is the lot-to-lot variation of the comparator window. An automatic window repositioning technique is detailed that allows to compensate the window shift. The components for the implementation comprising a reference comparator and the evaluation comparators are described along with the implementation of the technique. It is shown, that this technique allows the automatic lot condition adjustment of the evaluation comparators. Furthermore the technique can provide lot specific information to an automated test equipment that can be documented in the test results due to its diagnosis capability.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128690719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A CAD-oriented modeling approach of frequency-dependent behavior of substrate noise coupling for mixed-signal IC design 混合信号集成电路设计中基片噪声耦合频率依赖特性的cad建模方法
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194731
H. Lan, Zhiping Yu, R. Dutton
{"title":"A CAD-oriented modeling approach of frequency-dependent behavior of substrate noise coupling for mixed-signal IC design","authors":"H. Lan, Zhiping Yu, R. Dutton","doi":"10.1109/ISQED.2003.1194731","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194731","url":null,"abstract":"A simple, efficient CAD-oriented equivalent circuit modeling approach of frequency-dependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequency-dependent characteristics for high frequency applications using epitaxial layers on a highly doped substrate. Using the proposed modeling approach, circuit topographies consisting of only ideal lumped circuit elements can be synthesized to accurately represent the frequency response using y-parameters. The proposed model is well-suited for use in standard circuit simulators. The extracted model is shown to be in good agreement with rigorous 3D device simulation results.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128018099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
On structural vs. functional testing for delay faults 关于延迟故障的结构与功能测试
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194772
Angela Krstic, J. Liou, K. Cheng, Li-C. Wang
{"title":"On structural vs. functional testing for delay faults","authors":"Angela Krstic, J. Liou, K. Cheng, Li-C. Wang","doi":"10.1109/ISQED.2003.1194772","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194772","url":null,"abstract":"A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there could be a large difference in the number of structurally and functionally testable delay faults. However, this difference is usually calculated based only on logic constraints. It is unclear how this difference would change if timing constraints were taken into consideration, especially when using statistical timing models. In this paper, our goal is to better understand how structural and functional test strategies might affect the delay test quality and consequently, change our perception of the delay test results.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Modeling and analysis of power distribution networks for gigabit applications 千兆应用配电网络的建模与分析
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194737
Jinwoo Choi, S. Min, Joong-Ho Kim, M. Swaminathan, W. Beyene, Xingchao Yuan
{"title":"Modeling and analysis of power distribution networks for gigabit applications","authors":"Jinwoo Choi, S. Min, Joong-Ho Kim, M. Swaminathan, W. Beyene, Xingchao Yuan","doi":"10.1109/ISQED.2003.1194737","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194737","url":null,"abstract":"As the operating frequency of digital systems increases and voltage swing decreases, it becomes increasingly important to accurately characterize and analyze power distribution networks (PDN). This paper presents the modeling, simulation, and measurement of a PDN in a high-speed FR4 printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps and above. The test board consists of two transceiver chips placed on wire bond plastic ball grid array (PBGA) packages. The applied analysis method is a hybrid technique that combines the interactions of the power planes, interconnects, and the nonlinear drivers. The power planes and interconnects are modeled using the transmission matrix method (TMM) and rational interpolation, respectively. Then macro modeling is applied to generate reduced-order models to efficiently analyze the whole system including the nonlinear drivers using conventional circuit simulation tools such as SPICE. The transfer characteristics of the power planes are calculated and the effects of the decoupling capacitors and power supply noise are studied. The simulation results are also correlated with measurement data to verify the validity of the method.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128292948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
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