Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.最新文献_第7页

Interoperability beyond design: sharing knowledge between design and manufacturing 超越设计的互操作性:在设计和制造之间共享知识

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194734

D. Cottrell, T. J. Grebinski

{"title":"Interoperability beyond design: sharing knowledge between design and manufacturing","authors":"D. Cottrell, T. J. Grebinski","doi":"10.1109/ISQED.2003.1194734","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194734","url":null,"abstract":"The nature of IC design is necessarily evolving to a more data-centric design flow in which EDA tools share a common information in a design database without the negative cost and quality impacts of data translation from sequential files. In support of this new paradigm, a collection of mainstream companies within the IC supply chain have sponsored the development of an open industry data model and application program interface for IC design tools, along with a database that fully implements this. This technology, called OpenAccess, is now available and being adopted by the IC design community. Another industry effort is in operation with the goal of greatly improving the cost and efficiency for IC photomasks. That effort is exploring a new paradigm similar in nature to OpenAccess in that a common data model and data access language is proposed. This data model would span both the design and mask-making communities, and possibly expand into wafer fabrication over time. Thus, it has become known as the Universal Data Model (UDM). This paper discusses some of the rationale for the UDM and highlights the attributes of the OpenAccess technology that make it the ideal base on which to build an open industry UDM.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124393641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An embedded I/sub DDQ/ testing architecture and technique 嵌入式I/sub DDQ/测试体系结构和技术

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194773

Y. Tsiatouhas, T. Haniotakis, A. Arapoyanni

引用次数: 2

Cycle-accurate energy measurement and high-level energy characterization of FPGAs 周期精确的能量测量和fpga的高级能量表征

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194744

H. Lee, S. Nam, N. Chang

{"title":"Cycle-accurate energy measurement and high-level energy characterization of FPGAs","authors":"H. Lee, S. Nam, N. Chang","doi":"10.1109/ISQED.2003.1194744","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194744","url":null,"abstract":"Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to system-on-chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning, mapping, placement and route. While major CAD tools have started to report average power consumption under given transition activities, energy optimal FPGA design demands more detailed energy estimation. In this paper, we introduce an in-house cycle-accurate energy measurement tool and energy characterization schemes from low level to operation level. The tool offers all the necessary capability to investigate the energy consumption of FPGAs for high-level, operation-based energy characterization, which is useful for high-level, system-wide energy estimation. It also includes features for low-level energy characterization. We compare our tool with Xilinx XPower and demonstrate state machine energy characterization of an LCD controller and an SDRAM controller.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128989375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Is quality a design constraint for sub 100nm designs? 质量是100nm以下设计的约束吗?

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194700

S. Ohr

引用次数: 0

A proposal for routing-based timing-driven scan chain ordering 一种基于路由的定时驱动扫描链排序方法

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194755

Puneet Gupta, A. Kahng, S. Mantik

引用次数: 6

New DFM approach abstracts altPSM lithography requirements for sub-100 nm IC design domains 新的DFM方法抽象了亚100nm IC设计领域的altPSM光刻要求

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194721

Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, David Pinto

引用次数: 1

Reduced-order modeling based on Prony's and Shank's methods via the bilinear transformation 基于双线性变换的proony和Shank方法的降阶建模

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194749

M. Mansour, A. Mehrotra

引用次数: 1

The iFlow design factory: evolving chip design from an art to a process, through adaptive resource management, and qualified data exchange iFlow设计工厂:通过自适应资源管理和合格的数据交换，将芯片设计从艺术发展到过程

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194723

Gilles-Eric Descamps, S. Bagalkotkar, S. Ganesan, S. Subramaniam, H. Hingarh

{"title":"The iFlow design factory: evolving chip design from an art to a process, through adaptive resource management, and qualified data exchange","authors":"Gilles-Eric Descamps, S. Bagalkotkar, S. Ganesan, S. Subramaniam, H. Hingarh","doi":"10.1109/ISQED.2003.1194723","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194723","url":null,"abstract":"With advancing semiconductor technology, growing design complexities, companies have turned to a global design team to build their system on a chip (SoC). The major challenge is the capacity to scale infrastructure and methodology, along with ASIC design. Silicon Access Networks recently shipped for revenue from first silicon, a family of four high performance SoC products. These high-end networking products were designed in state-of-the-art 0.13 /spl mu/m process and collectively had about 750-million transistors and a variety of analog, digital and memory functional blocks to provide the industry's highest performance OC-192 Data Plane Processing solution. This paper describes some of the key aspects of Silicon Access Networks' design methodology that enabled to accomplish repeatable \"first pass silicon\" successes. We gained predictability in our chip design cycle through real-time visibility of the processes. Quality enhancing strategies were applied to the chip design cycles. Adaptive resource management, and qualified data exchange were the two main techniques. Multi site design teams working in different time zones may be a pitfall, or may allow for true 24/7 operation, depending on whether the right data and resources are available. Building such large designs in parallel requires efficient management of resources - machines, tools and users - in a transparent but truly global environment.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132977660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing the energy-delay-ringing product in on-chip CMOS line drivers 片上CMOS线路驱动器中能量延迟振铃产品的优化

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI: 10.1109/ISQED.2003.1194743

S. Abbaspour, Massoud Pedram, P. Heydari

引用次数: 1

Proceedings Fourth International Symposium on Quality Electronic Design 第四届质量电子设计国际研讨会论文集

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2003.1194698

引用次数: 9