Is quality a design constraint for sub 100nm designs?

Deep sub-micron design (below 100nm) present a number of new design challenges. These include very high masking costs, new interconnect materials and parasitic phenomenon, significant re-engineering at the device level due to changes in basic device performance, very high gate count and pin count designs, complexity in high pin count packaging & test, and finally reduced product life in the marketplace do to the rapid rollout of new technologies. One of the trade offs that is taking place in the industry to address these issues is the decision toward “design existence”, which is the selection of the “first functional implementation” of a design, over “design quality” which is the selection of the “optimal implementation” of a design.