嵌入式I/sub DDQ/测试体系结构和技术

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. Pub Date : 2003-03-24 DOI:10.1109/ISQED.2003.1194773

Y. Tsiatouhas, T. Haniotakis, A. Arapoyanni

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引用次数: 2

摘要

本文提出了一种嵌入式I/sub DDQ/测试体系结构，旨在克服基于内置电流传感的测试应用中过多的硬件开销要求。此外，还提供了一种利用IEEE 1149.1边界扫描标准来控制所提出的体系结构的技术。所提出的解决方案的特点是硅面积要求低，并且允许在芯片安装在印刷电路板上的情况下应用I/sub DDQ/测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An embedded I/sub DDQ/ testing architecture and technique

In this paper an embedded I/sub DDQ/ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permits the application of I/sub DDQ/ testing also in case that the chip is mounted on a printed circuit board.

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Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

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