An embedded I/sub DDQ/ testing architecture and technique

Abstract

In this paper an embedded I/sub DDQ/ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permits the application of I/sub DDQ/ testing also in case that the chip is mounted on a printed circuit board.