The iFlow design factory: evolving chip design from an art to a process, through adaptive resource management, and qualified data exchange

With advancing semiconductor technology, growing design complexities, companies have turned to a global design team to build their system on a chip (SoC). The major challenge is the capacity to scale infrastructure and methodology, along with ASIC design. Silicon Access Networks recently shipped for revenue from first silicon, a family of four high performance SoC products. These high-end networking products were designed in state-of-the-art 0.13 /spl mu/m process and collectively had about 750-million transistors and a variety of analog, digital and memory functional blocks to provide the industry's highest performance OC-192 Data Plane Processing solution. This paper describes some of the key aspects of Silicon Access Networks' design methodology that enabled to accomplish repeatable "first pass silicon" successes. We gained predictability in our chip design cycle through real-time visibility of the processes. Quality enhancing strategies were applied to the chip design cycles. Adaptive resource management, and qualified data exchange were the two main techniques. Multi site design teams working in different time zones may be a pitfall, or may allow for true 24/7 operation, depending on whether the right data and resources are available. Building such large designs in parallel requires efficient management of resources - machines, tools and users - in a transparent but truly global environment.