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2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献

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2.4 Hz–5 kHz Passband $11.8 mu mathrm{V}_{text{RMS}}$ Noise Power Neural Amplifier for Brain-Chip Interfaces 2.4 hz - 5khz通带$11.8 mu mathm {V}_{text{RMS}}$用于脑芯片接口的噪声功率神经放大器
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665636
E. Vallicelli, A. Baschirotto, Lorenzo Stevenazzi, Luciano Rota, M. Matteis
{"title":"2.4 Hz–5 kHz Passband $11.8 mu mathrm{V}_{text{RMS}}$ Noise Power Neural Amplifier for Brain-Chip Interfaces","authors":"E. Vallicelli, A. Baschirotto, Lorenzo Stevenazzi, Luciano Rota, M. Matteis","doi":"10.1109/icecs53924.2021.9665636","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665636","url":null,"abstract":"This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of $mathrm{G}Omega$ order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing $7.8 mu mathrm{V}_{text{RMS}}$ and $8.8 mu mathrm{V}_{text{RMS}}$ input-referred noise power at 1 Hz – 300 Hz (Local Field Potential) and 300 Hz–5 kHz (Action Potentials) bandwidth, respectively. The device consumes $2.4 mu mathrm{W}$ power and has been designed in 28 nm CMOS technology.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129088999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Detecting denial-of-service hardware Trojans in DRAM-based memory systems 在基于dram的内存系统中检测拒绝服务硬件木马
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665634
Heba Salem, N. Topham
{"title":"Detecting denial-of-service hardware Trojans in DRAM-based memory systems","authors":"Heba Salem, N. Topham","doi":"10.1109/icecs53924.2021.9665634","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665634","url":null,"abstract":"DRAM latencies are inherently variable, potentially allowing a denial-of-service hardware Trojan (DoS HT) to degrade memory performance without becoming immediately obvious. This paper addresses the challenge of detecting a DoS HT that may have been inserted into a DRAM-based memory system, without requiring detailed internal knowledge of the DRAM device. We present a real-time machine-learning based DoS HT detection technique based on a low-cost hardware monitor at the interface to the DRAM controller, coupled with periodic software based analysis of monitoring output.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Resolution Requirements in 0-X MASH Delta-Sigma-Modulators 0-X MASH delta - sigma调制器的数字分辨率要求
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/ICECS53924.2021.9665539
Jonathan Ungethüm, John G. Kauffman, M. Ortmanns
{"title":"Digital Resolution Requirements in 0-X MASH Delta-Sigma-Modulators","authors":"Jonathan Ungethüm, John G. Kauffman, M. Ortmanns","doi":"10.1109/ICECS53924.2021.9665539","DOIUrl":"https://doi.org/10.1109/ICECS53924.2021.9665539","url":null,"abstract":"The 0-X multi-stage noise-shaping (MASH) Delta-Sigma-modulator is a possible implementation of a continuous-time (CT) pipeline ADC. One of the main implementation challenges is the matching between the analog and digital signal paths. Since the power consumption of the noise cancellation filter (NCF) becomes significant for high-speed and high-accuracy applications, an estimation of the required accuracy inside the NCF is desirable to give an insight into the prospective overall system complexity. Furthermore, analog mismatches may limit the ADC's performance. This paper shows, that architectures can be found, which relax the coefficient resolution requirement in the NCF thereby facilitating its implementation.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders 5G新型无线电LDPC解码器的增强校验节点架构
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665587
Ghaffari Fakhreddine, K. Le
{"title":"An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders","authors":"Ghaffari Fakhreddine, K. Le","doi":"10.1109/icecs53924.2021.9665587","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665587","url":null,"abstract":"This paper presents an efficient hardware architecture of the Check Node (CN) units for the fifth generation (5G) new-radio Low-Density Parity-Check (LDPC) decoders. The proposed CN architecture is designed by splitting the high-degree CN operations into several phases and simplifying computing circuitry and connection wires. The critical path is shortened while the latency increment for one decoding iteration is negligible. Also, the proposed architecture allows to apply adaptively different offset factors when decoding different CN degree. This technique enhances the error rate and performance of our quantized LDPC decoder. The ASIC synthesis results confirm the advantages of the proposed architecture. This later helps reduce the decoder complexity by up to 30% while the operating frequency is enhanced by 10% compared to the conventional solution.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"52 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120935027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks 空间应用中的FPGA和VPU协同处理:DSP/AI基准的开发和测试
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665462
Vasileios Leon, Charalampos Bezaitis, G. Lentaris, D. Soudris, D. Reisis, E. Papatheofanous, A. Kyriakos, A. Dunne, A. Samuelsson, D. Steenari
{"title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","authors":"Vasileios Leon, Charalampos Bezaitis, G. Lentaris, D. Soudris, D. Reisis, E. Papatheofanous, A. Kyriakos, A. Dunne, A. Samuelsson, D. Steenari","doi":"10.1109/icecs53924.2021.9665462","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665462","url":null,"abstract":"The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for onboard data processing. We examine heterogeneous computing architectures involving high-performance and low-power commercial SoCs. The current paper implements an FPGA with VPU co-processing architecture utilizing the CIF & LCD interfaces for I/O data transfers. A Kintex FPGA serves as our framing processor and heritage accelerator, while we offload novel DSP/AI functions to a Myriad2 VPU. We prototype our architecture in the lab to evaluate the interfaces, the FPGA resource utilization, the VPU computational throughput, as well as the entire data handling system's performance, via custom benchmarking.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131009262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC 无显式输出锁存级的高速SoC动态差分触发器
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665559
Min-su Kim, W. Choi, Jong-Woo Kim, Chunghee Kim, Jae-Hyuk Oh, B. Kong
{"title":"Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC","authors":"Min-su Kim, W. Choi, Jong-Woo Kim, Chunghee Kim, Jae-Hyuk Oh, B. Kong","doi":"10.1109/icecs53924.2021.9665559","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665559","url":null,"abstract":"In this paper, a novel high-speed dynamic differential flip-flop to provide an edge-triggered operation without an explicit output latching stage is proposed. Due to the elimination of the output latching stage, the proposed differential flip-flop can provide a significantly reduced falling data-to-output (DQ) latency and even a negative rising DQ latency under a certain condition. A novel pipelining scheme with the proposed flip-flops is also proposed to exploit the negative latency feature to further improve the switching performance. The comparison results in a 65 nm CMOS process indicate that the worst-case DQ latency of the proposed flip-flop is reduced by up to 61% and the energy-delay product is improved by up to 69% as compared to conventional differential flip-flops. The results also indicate that the throughput provided by the proposed pipelining scheme is improved by up to 21%.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128693601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.2-MS/s 14-Bit Extended-Range Second-Order Incremental ADC 一个3.2 ms /s的14位扩展范围二阶增量ADC
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665647
Abhijeet D. Taralkar, F. Conzatti, P. Malcovati, A. Baschirotto
{"title":"A 3.2-MS/s 14-Bit Extended-Range Second-Order Incremental ADC","authors":"Abhijeet D. Taralkar, F. Conzatti, P. Malcovati, A. Baschirotto","doi":"10.1109/icecs53924.2021.9665647","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665647","url":null,"abstract":"This paper presents a 14-bits two-stage extended-range A/D converter (ERADC), consisting of a switched-capacitor second-order incremental ADC (IADC) based on a cascade of integrators with feedforward topology as first stage, followed by a 5-bit SAR ADC as second stage. The proposed architecture, does not require any active inter-stage block for providing the residue of the IADC coarse conversion to the SAR ADC for fine conversion, thus minimizing the power consumption. This is achieved by gating the IADC feedforward paths during the last clock cycle of the IADC conversion. With a clock frequency of 80 MHz, the complete ERADC achieves in simulation a peak SNR of 86 dB and a dynamic range of 92 dB at a data rate of 3.2 MS/s (24 clock cycles per conversion).","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128751393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microarchitecture Optimization for Asynchronous Stochastic Computing 异步随机计算的微架构优化
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665644
R. Sreekumar, M. Stan
{"title":"Microarchitecture Optimization for Asynchronous Stochastic Computing","authors":"R. Sreekumar, M. Stan","doi":"10.1109/icecs53924.2021.9665644","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665644","url":null,"abstract":"Asynchronous Stochastic Computing (ASC) is a branch of clockless Stochastic Computing methodology that encodes signals as a digital asynchronous pulse-width modulated stream that carries information within it's duty cycle and frequency. In this paper a comprehensive study into the energy and frequency optimization of Asynchronous Stochastic Computing circuits is presented. Design knobs that affect characteristics of the stream are identified and, by evaluating their sensitivity, a Pareto optimization strategy is derived. In distributed computing systems such as wearable sensors, dynamic throughput scaling is often required. The insights from the Pareto analysis, are utilized to design a scalable throughput Asynchronous Stochastic Computing Arithmetic unit, that is capable of performing Multiply-Accumulate (MAC) operations. Our simulated results in the design of the arithmetic unit prove the effectiveness of the single optimization problem through an average energy savings of 17- 32% across the two different throughput regions of operation.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131209449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison of Different Implementation Methods of Fractional-Order Derivative/Integral 分数阶导数/积分不同实现方法的比较
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665512
Alaa AbdAlRahman, A. Soltan, A. Radwan
{"title":"Comparison of Different Implementation Methods of Fractional-Order Derivative/Integral","authors":"Alaa AbdAlRahman, A. Soltan, A. Radwan","doi":"10.1109/icecs53924.2021.9665512","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665512","url":null,"abstract":"Implementing a fractional-order operator requires many resources to acquire an accurate response compared to the theoretical response. In this paper, three implementation methods of digital fractional-order operators are exploited. The three implementation methods are based on FIR, IIR, and lattice wave digital filters. The three methods are implemented using different optimization algorithms to optimize the choice of the coefficients of the three filters. This optimization is done to approximate the frequency response of an ideal fractional operator. This comparison aims to determine each implementation method's accuracy and resource usage level to decide which method is better for different systems.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126863062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS 全数字VCO-ADC TAD用16nm FinFET CMOS确认缩放和随机效应
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665569
Takamoto Watanabe
{"title":"All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS","authors":"Takamoto Watanabe","doi":"10.1109/icecs53924.2021.9665569","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665569","url":null,"abstract":"A concept of an all-digital ADC for technology scaling with a non-interleaved 10-GS/s VCO-based Time-A/D converter (TAD) is proposed. A complementary-ring-delay-line setup (c-RDL) simply realizes uncorrelated conditions between two TADs with a stochastic effect, resulting in being ideally scalable because of the all-digital configuration. TAD speed and resolution can inevitably be improved along with finer technologies, confirmed in a 16-nm FinFET CMOS compared to 800 to 40-nm CMOS nodes. Due to its small core area in a 16-nm CMOS, a TAD-core parallel method is compactly developed using a 4-clock-edge-shift (4CKES) type with one ring-delay-line (RDL) shared by four TAD-logic modules (TMs) with effectively modified encoders. Using post-layout simulation, the 4CKES-type-TAD with c-RDL produces 6.9-bit resolution, 3.5-ENOB and 0.0077 mm2 without any calibration with its 4-times-higher resolution compared to a single-type.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124608895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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