Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC

In this paper, a novel high-speed dynamic differential flip-flop to provide an edge-triggered operation without an explicit output latching stage is proposed. Due to the elimination of the output latching stage, the proposed differential flip-flop can provide a significantly reduced falling data-to-output (DQ) latency and even a negative rising DQ latency under a certain condition. A novel pipelining scheme with the proposed flip-flops is also proposed to exploit the negative latency feature to further improve the switching performance. The comparison results in a 65 nm CMOS process indicate that the worst-case DQ latency of the proposed flip-flop is reduced by up to 61% and the energy-delay product is improved by up to 69% as compared to conventional differential flip-flops. The results also indicate that the throughput provided by the proposed pipelining scheme is improved by up to 21%.