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2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献

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Power- and Area-optimized Neural Network IC-Design for Academic Education 面向学术教育的功率和面积优化神经网络集成电路设计
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665471
Florian Frankreiter, A. Breitenreiter, O. Schrape, M. Krstic
{"title":"Power- and Area-optimized Neural Network IC-Design for Academic Education","authors":"Florian Frankreiter, A. Breitenreiter, O. Schrape, M. Krstic","doi":"10.1109/icecs53924.2021.9665471","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665471","url":null,"abstract":"A shortage of practically skilled computer science graduates affects academia as well as the industry. Especially when it comes to hardware design and awareness about the complete digital design flow, a lack of qualified personell can hinder the progess of development teams. To address this issue, we will present the design of an integrated circuit (IC) containing a power- and area optimized neural network, enabling know-how development of the students various key skills required for hardware design. This example project, targeting bachelor and master students interested in hardware engineering and artificial intelligence, offers learning potential in various fields and enough room for creative design decisions and detailed discussions. Possible design options and improvements are discussed throughout the paper with focus on their educational aspects.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120847413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental Measurements of an Integrated Hysteretic Controlled Regulating Buck Converter with Capacitively Coupled Bootstrapping 电容耦合自举集成滞回控制调节降压变换器的实验测量
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665602
Francarl Galea, O. Casha, I. Grech, E. Gatt, J. Micallef
{"title":"Experimental Measurements of an Integrated Hysteretic Controlled Regulating Buck Converter with Capacitively Coupled Bootstrapping","authors":"Francarl Galea, O. Casha, I. Grech, E. Gatt, J. Micallef","doi":"10.1109/icecs53924.2021.9665602","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665602","url":null,"abstract":"This paper presents the complete measured performance and characterization of an on-chip regulating buck converter with hysteretic control. The circuit was fabricated using the XFAB CMOS $0.35 mu mathrm{m}$ high voltage technology and all the control circuit blocks were designed using analog techniques, with the transistors operating in the sub-threshold region, in order to minimize power consumption. All the high voltage transistors of the buck converter were implemented using 45V NMOS thin gate oxide layer transistors and are operated by means of a capacitively coupled bootstrap. The control circuit of the hysteretic regulator consumes between $194 mumathrm{W}$ and $420 mu mathrm{W}$, and the proposed buck converter operates at a peak efficiency of 84.2%. The input voltage range of the regulator is from 1.5V to 45V and has a power range from $100 mu mathrm{W}$ to 500 mW. The output regulated voltage is tunable via a feedback resistor and can be varied from 0.6V to 40 V, with a dropout voltage of 2 V.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116478768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy Efficient Approximate 4:2 Compressors for Error Tolerant Applications 节能约4:2压缩机容错应用
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665614
L. Krishna, J. B. Rao, Ayesha Sk, S. Veeramachaneni, S. Mahammad
{"title":"Energy Efficient Approximate 4:2 Compressors for Error Tolerant Applications","authors":"L. Krishna, J. B. Rao, Ayesha Sk, S. Veeramachaneni, S. Mahammad","doi":"10.1109/icecs53924.2021.9665614","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665614","url":null,"abstract":"In many real-life applications such as image/video processing, the error present in the output will not impact the output visual information. Approximation at the hardware level is one of the promising techniques to design energy-efficient circuits. This paper proposes an approximate 4:2 compressor design to reduce partial products in the multiplier design. The proposed approximate 4:2 compressor design consumes on an average 56% less energy compared with the existing designs from the literature, respectively. This paper proposes two variants of the approximate multiplier designs, where design1 uses only proposed approximate 4:2 compressors and multiplier design2's lower half of the multiplier is designed using proposed approximate 4:2 compressor and higher half of the multiplier is designed using existing accurate compressors to reduce the error rate and improve the output image visual quality.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129850144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wearable Low-power Closed-loop System for Tremor Detection and Stimulation using Electromyography (EMG) 基于肌电图(EMG)的可穿戴低功耗闭环震颤检测与刺激系统
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665556
Muhammad Rizwan Khan, Wala Saadeh, Muhammad Awais Bin Altaf
{"title":"Wearable Low-power Closed-loop System for Tremor Detection and Stimulation using Electromyography (EMG)","authors":"Muhammad Rizwan Khan, Wala Saadeh, Muhammad Awais Bin Altaf","doi":"10.1109/icecs53924.2021.9665556","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665556","url":null,"abstract":"A wearable EMG based tremor detection and suppression system is presented. This work proposes a novel design enabling low-power consumption, wearability, lower computational cost and lower latency. An analog front end (AFE) is designed containing cascaded filters and a Driven-Right-Leg (DRL) feedback for high-level noise removal of up to 1V. A CC1352R microcontroller with an integrated BLE along with RTOS is utilized to achieve low-power processing. A user-friendly interface is provided using Android application (AP) that allows immediate sharing of data to caretakers or database. A 128-point FFT is employed with a simple implementation in terms of computation and a variable-voltage skin-impedance based muscle stimulation is being used. The system is operable on coin cell batteries for more than 3 weeks. The overall average power consumption of the system is 4.8mW with average current 1.35mA and a detection latency of <0.2s is achieved.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"85 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125717343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area estimation circuit for Weigh-In-Motion applications using piezoelectric transducers 基于压电换能器的运动称重面积估计电路
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665543
Zoi Agorastou, V. Gogolou, Konstantinos Kozalakis, S. Siskos
{"title":"Area estimation circuit for Weigh-In-Motion applications using piezoelectric transducers","authors":"Zoi Agorastou, V. Gogolou, Konstantinos Kozalakis, S. Siskos","doi":"10.1109/icecs53924.2021.9665543","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665543","url":null,"abstract":"An ultra-low power, piezoelectric sensor interface circuit for Weigh-In-Motion applications is presented. It is optimized for energy-autonomous vehicle-weight measuring systems in road monitoring applications and can be combined with any type and size of piezoelectric device. Whenever the output voltage of the used piezoelectric sensor exceeds a predefined threshold level, the circuit is activated, measuring the voltage area integral of the detected pulse. A low-power microcontroller unit can be used for the calculation and use of the obtained weight measurements. The circuit was implemented with a combination of discrete analog circuits for the activation and duration units, as well as an integrated voltage-to-frequency converter for the area-integral calculation.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"430 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131965698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual Output Regulating Rectifier for an Implantable Neural Interface 用于植入式神经接口的双输出调节整流器
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665613
Noora Almarri, D. Jiang, A. Demosthenous
{"title":"Dual Output Regulating Rectifier for an Implantable Neural Interface","authors":"Noora Almarri, D. Jiang, A. Demosthenous","doi":"10.1109/icecs53924.2021.9665613","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665613","url":null,"abstract":"This paper presents the design of a power management circuit consisting of a dual output regulating rectifier configuration featuring pulse width modulation (PWM) and pulse frequency modulation (PFM) to control the regulated output of 1.8 V, and 3.3 V from a single input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through the buffers in the active rectifier. The PWM mode control provides a feedback loop to accurately adjust the conduction duration. The design also includes an adiabatic charge pump (CP) to power stimulators in an implantable neural interface. The adiabatic CP consists of latch up and power saving topologies to enhance its energy efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power transfer efficiency of the regulated 3.3 V output voltage is 82.3%. The dual output regulating rectifier topology is suitable for multi-functional implantable devices. The adiabatic CP has an overall efficiency of 92.9% with an overall on-chip capacitance of 60 pF. The circuit was designed in a 180-nm CMOS technology.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"168 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113987811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.2V 0.97nW 0.011mm2 Fully-Passive mHBC Tag Using Intermediate Interference Modulation in 65nm CMOS 采用65nm CMOS中间干扰调制的0.2V 0.97nW 0.011mm2全无源mHBC标签
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665542
A. Tanaka, Guowei Chen, Sitong Ye, K. Niitsu
{"title":"A 0.2V 0.97nW 0.011mm2 Fully-Passive mHBC Tag Using Intermediate Interference Modulation in 65nm CMOS","authors":"A. Tanaka, Guowei Chen, Sitong Ye, K. Niitsu","doi":"10.1109/icecs53924.2021.9665542","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665542","url":null,"abstract":"A low-power and small-form-factor fully-passive magnetic human body communication (mHBC) tag in 65nm CMOS for low-cost biomedical IoT application is presented. By employing a newly proposed intermediate interference modulation technique, the full-passive mHBC scheme can emerge, which enables battery-less and low-power operation. The tag circuit with an NMOS-stacked LDO regulator, a differential ring oscillator, and a level shifter has also been proposed for further power reduction and footprint reduction. The prototype chip of 0.011mm2 was developed in 65nm standard CMOS. The measurement results showed successful operation with 0.97nW under 0.2V.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114718493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-cost IoT-based device to measure exposure to sub-6GHz 5G waves 一种基于物联网的低成本设备，用于测量6ghz以下5G波的暴露
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/ICECS53924.2021.9665585
L. Guenego, F. Rivet, G. Ferré, Anouar Walzik, Aharram Souhayl, Amine Karbab
{"title":"A low-cost IoT-based device to measure exposure to sub-6GHz 5G waves","authors":"L. Guenego, F. Rivet, G. Ferré, Anouar Walzik, Aharram Souhayl, Amine Karbab","doi":"10.1109/ICECS53924.2021.9665585","DOIUrl":"https://doi.org/10.1109/ICECS53924.2021.9665585","url":null,"abstract":"The electromagnetic radiations impact on human beings is a controversial topic ever since the announcement of the 5G network deployment. This article presents a connected object to gather power measurements of the new 5G n78 band in France using low-cost components off-the-shelf (COTS). This object delivers to the user a 5G network exposure risk evaluation, comparing processed data to reference levels from medical studies and laws regarding the exposure to electromagnetic radiations. The results of this study demystify the general public exposure to 5G radiations from the n78 band.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128059481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exploring the analytical boundaries of capacitive feedback transimpedance amplifiers 探索电容反馈跨阻放大器的分析边界
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665553
Quentin Schmidt, A. Morel, Yasser Moursy, Houssein Elmi Dawale, G. Billiot, F. Badets
{"title":"Exploring the analytical boundaries of capacitive feedback transimpedance amplifiers","authors":"Quentin Schmidt, A. Morel, Yasser Moursy, Houssein Elmi Dawale, G. Billiot, F. Badets","doi":"10.1109/icecs53924.2021.9665553","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665553","url":null,"abstract":"This paper proposes a comprehensive model of capacitive feedback transimpedance amplifiers, based on an analysis of the parasitics and non-idealities of the system. The proposed model is in good agreement with circuit simulations (less than 2% error on the gain and 18% on the bandwidth for large set of parameters), and allows to compute the analytical boundaries of the capacitive topology. Finally, a comparative assessment between capacitive and resistive topologies in terms of performance is proposed and highlights the salient performances of capacitive feedback transimpedance amplifiers.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133310661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhancing Security in the Industrial IoT Sector using Quantum Computing 利用量子计算增强工业物联网领域的安全性
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665527
Syed Farhan Ahmad, Mohamed Yassine Ferjani, Keshav Kasliwal
{"title":"Enhancing Security in the Industrial IoT Sector using Quantum Computing","authors":"Syed Farhan Ahmad, Mohamed Yassine Ferjani, Keshav Kasliwal","doi":"10.1109/icecs53924.2021.9665527","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665527","url":null,"abstract":"The development of edge computing and machine learning technologies have led to the growth of Industrial IoT systems. Autonomous decision making and smart manufacturing are flourishing in the current age of Industry 4.0. By providing more compute power to edge devices and connecting them to the internet, the so-called Cyber Physical Systems are prone to security threats like never before. Security in the current industry is based on cryptographic techniques that use pseudorandom number keys. Keys generated by a pseudo-random number generator pose a security threat as they can be predicted by a malicious third party. In this work, we propose a secure Industrial IoT Architecture that makes use of true random numbers generated by a quantum random number generator (QRNG). CITRIOT's FireConnect IoT node is used to show the proof of concept in a quantum-safe network where the random keys are generated by a cloud based quantum device. We provide an implementation of QRNG on both real quantum computer and quantum simulator. Then, we compare the results with pseudorandom numbers generated by a classical computer.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127218189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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