2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献_第7页

A Class AB Programmable Gain Amplifier for an UWB Breast Cancer Detection System 用于超宽带乳腺癌检测系统的AB类可编程增益放大器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665475

T. Martins, David Reyes, B. Sanches, W. Noije

引用次数: 2

An Implantable 8-Contact Sense and Stimulation System for Continuous Recording 一种可植入的连续记录8触点传感和刺激系统

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/ICECS53924.2021.9665529

John Gahnz, Justin Doerr, Heather Orser

引用次数: 0

Efficient Standard-Cell Legalization for Minimization of Total Movement 有效的标准细胞合法化，最大限度地减少总运动

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665563

Jin-Tai Yan, Po-Yuan Huang, Chia-Hsun Yen

引用次数: 1

CNN Inference Costs Estimation on Microcontrollers: the EST Primitive-based Model 微控制器的CNN推理成本估计:基于EST原语的模型

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665540

Thomas Garbay, Petr Dobiáš, Wilfried Dron, Pedro Lusich, Imane Khalis, A. Pinna, K. Hachicha, B. Granado

{"title":"CNN Inference Costs Estimation on Microcontrollers: the EST Primitive-based Model","authors":"Thomas Garbay, Petr Dobiáš, Wilfried Dron, Pedro Lusich, Imane Khalis, A. Pinna, K. Hachicha, B. Granado","doi":"10.1109/icecs53924.2021.9665540","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665540","url":null,"abstract":"Neural network inference on embedded devices will have an important industrial impact on our society. Embedded devices are ubiquitous in many fields, like human activity recognition or visual object detection. As a matter of fact, Convolutional Neural Networks (CNNs) are now the best modality to solve most of computer vision problems. Although, the accuracy offered by these algorithms has a cost: an important energy consumption, a high execution time, and a significant memory footprint. This cost is a major challenge to implement CNNs within embedded devices with limited computational power, memory space and energy available. This makes prior estimation about the impact of a CNN on a given microcontroller, a design key point before applying neural network compression techniques. We introduce the EST primitive-based model to estimate the impact of a CNN on a microcontroller, regarding the latency, the power consumption and the needed memory space. The target hardware is the STM32L496ZG with CPU ARM Cortex M4 running at 14 different frequencies. Our model shows an average estimation error of 13.66% on latency, 5.52% on power consumption and 2.09% on needed memory space.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124451965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications 5G毫米波应用中使用后门体偏置的模拟占空比控制器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665600

C. Beauquier, D. Duperray, C. Jabbour, P. Desgreys, A. Frappé, A. Kaiser

引用次数: 0

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop 超低功耗，低功耗静态单相时钟触发器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665485

Yugal Maheshwari, Kleber Stangherlin, Derek Wright, M. Sachdev

引用次数: 2

Analysis of Blackhole Attack in RPL-based 6LoWPAN Network: A Case Study 基于rpl的6LoWPAN网络黑洞攻击分析

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665623

V. Rajasekar, S. Rajkumar

{"title":"Analysis of Blackhole Attack in RPL-based 6LoWPAN Network: A Case Study","authors":"V. Rajasekar, S. Rajkumar","doi":"10.1109/icecs53924.2021.9665623","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665623","url":null,"abstract":"A Blackhole attack is a network isolation attack in which a malicious node discards all packets intended for forwarding. The presence of a Blackhole node increases the number of DIO packets which indicates network topology is unstable, whereas decreased DIO messages indicate a stable network. This paper examines the impact of a single Blackhole attack and colluding Blackhole attack on a 6LoWPAN network using four distinct scenarios, each with its own set of test cases. In a single Blackhole attack, the PDR decreases by up to 7.72%, the delay increases by 372.62%, the average power consumption increases by 122.58%, and the number of DIO messages increase 19.35% compared to the reference topology. Compared to the reference topology, the colluding Blackhole attack results in a maximum of 9.12% in PDR, a 549.65% increase in delay, a 170.98% increase in average power consumption, and a 25.6% increase in the number of DIO messages. The simulation results indicate that increasing the number of attacker nodes and their placement has a noticeable negative effect on the network performance. This study will aid researchers in developing a robust defense system for RPL-based networks against Blackhole attacks.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131303015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart SoCs 一种用于智能soc的6.5 nA静态自校准可编程电压基准

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665463

Michele Caselli, E. Tiurin, S. Stanzione, A. Boni

引用次数: 3

Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits 检测流水线电路中拒绝服务木马的形式化验证方法

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665617

Kushal K. Ponugoti, S. Srinivasan, Nimish Mathure

引用次数: 0

On Reducing the Number of Multiplications in RNS-based CNN Accelerators 关于减少基于神经网络的CNN加速器的乘法次数

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/ICECS53924.2021.9665461

Vasilis Sakellariou, Vassilis Paliouras, I. Kouretas, H. Saleh, T. Stouraitis

{"title":"On Reducing the Number of Multiplications in RNS-based CNN Accelerators","authors":"Vasilis Sakellariou, Vassilis Paliouras, I. Kouretas, H. Saleh, T. Stouraitis","doi":"10.1109/ICECS53924.2021.9665461","DOIUrl":"https://doi.org/10.1109/ICECS53924.2021.9665461","url":null,"abstract":"In this paper, a method to reduce the number of multiplications in Convolutional Neural Networks (CNNs) by exploiting the properties of the Residue Number System (RNS) is proposed. RNS decomposes the elementary computations into a number of small bit-width, independent channels, which can be processed in parallel. Naturally, due to the small dynamic range of each RNS channel, the number of common factors inside the weight kernels during a convolution is increased. By identifying these common factors and by rearranging the order of computations to perform first the additions of the input feature-map terms that correspond to the same factors, the number of multiplications can be reduced up to 97 %, for state-of-the-art CNN models. The remaining multiplications are also simplified, as they are implemented through shift-add operations or fixed-operand multipliers. ASIC implementations of the proposed Processing Element (PE) architecture show a speedup of up to 2.67× and 1.64× compared to the binary and conventional RNS counterparts, respectively. Compared to a conventional RNS PE implementation, the proposed method also leads to a 20% reduction in area and 16% reduction in power consumption.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"15 20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124736914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2