Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

Abstract

Flip-flops are a key component of digital integrated circuits and substantially affect their power and energy consumption. In this paper, an ultra low-power, contention-free, static single-phase 3-transistors clock load flip-flop is described and referred to as 19-T Ultra Low-power Flip-flop (ULFF). Simulation results in CMOS 65 nm technology show that at nominal conditions and Data Activity (DA) of 10%, the ULFF has 56% and 7% low-power consumption compared to the 18-T Single-phase Clocked Static Flip-flop (18TSPC), and Topologically Compressed Flip-flop (TCFF), respectively. Similarly, ULFF has energy-efficiency comparable to Low-power at Low-data activity Flip-flop (LLFF) at low DAs, and 18TSPC at high DAs.