2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献_第6页

Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations 用算术近似提高谐波消除VLSI架构的效率

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665538

Patrícia U. L. da Costa, P. Pereira, Guilherme Paim, E. Costa, S. Bampi

{"title":"Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations","authors":"Patrícia U. L. da Costa, P. Pereira, Guilherme Paim, E. Costa, S. Bampi","doi":"10.1109/icecs53924.2021.9665538","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665538","url":null,"abstract":"Approximate computing emerged as a key alternative for trading off accuracy against energy efficiency and area reduction. Error-tolerant applications, such as multimedia processing, machine learning, and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level. Adaptive filtering-based systems have been demonstrating high resiliency against hardware errors due to their intrinsic self-healing characteristic. This paper investigates the design space exploration of arithmetic approximations in a Very Large-Scale Integration (VLSI) harmonic elimination (HE) hardware architecture based on Least Mean Square (LMS) adaptive filters. We evaluate the Pareto front of the area- and power versus quality curves by relaxing the arithmetic precision and by adopting both approximate multipliers (AxMs) in combination with approximate adders (AxAs). This paper explores the benefits and impacts of the Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), and Leading one Bit-based Approximate (LoBA) multipliers in the power dissipation, circuit area, and quality of the VLSI HE architectures. Our results highlight the LoBA 0 as the most efficient AxM applied in the HE architecture. We combine the LoBA 0 with Copy and LOA AxAs with variations in the approximation level (L). Notably, LoBA 0 and LOA with $L=6$ resulted in savings of 43.7% in circuit area and 45.2% in power dissipation, compared to the exact HE, which uses multiplier and adder automatically selected by the logic synthesis tool. Finally, we demonstrate that the best hardware architecture found in our investigation successfully eliminates the contaminating spurious noise (i.e., 60 Hz and its harmonics) from the signal.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133264783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Wideband Low Noise Amplifiers for mm-Wave 5G Application using Capacitive Feedback Technique in 22nm FDSOI 基于电容反馈技术的22nm FDSOI毫米波5G宽带低噪声放大器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665531

A. Mustapha, Sagiru Gaya, B. Mohammad, M. Abou-Khousa

引用次数: 0

Noise-aware design methodology of ultra-low-noise transimpedance amplifiers 超低噪声跨阻放大器的噪声感知设计方法

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665532

Ayman Mohamed, D. Djekic, Lars Baumgärtner, J. Anders

引用次数: 0

Keyword Spotting System using Low-complexity Feature Extraction and Quantized LSTM 基于低复杂度特征提取和量化LSTM的关键词识别系统

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665486

Kevin Herisse, Benoît Larras, A. Frappé, Andreas Kaiser

引用次数: 0

Ultra Wideband 43 GHz Preamplifier with up to 60 dB adjustable Gain for accurate Noise Figure Measurement of Cryogenic LNAs 超宽带43 GHz前置放大器，可调增益高达60 dB，用于低温LNAs的精确噪声系数测量

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665628

Peter Toth, M. Tiesing, Lukas Naumann, Andreas Fröhlich, Thomas Wirths, P. Knott

{"title":"Ultra Wideband 43 GHz Preamplifier with up to 60 dB adjustable Gain for accurate Noise Figure Measurement of Cryogenic LNAs","authors":"Peter Toth, M. Tiesing, Lukas Naumann, Andreas Fröhlich, Thomas Wirths, P. Knott","doi":"10.1109/icecs53924.2021.9665628","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665628","url":null,"abstract":"Noise-sensitive applications such as scaleable control electronics for quantum computing or RADAR systems for space debris detection require a high signal-to-noise ratio (SNR) to achieve the necessary sensitivity. Cryo cooling of the frontend electronics is a suitable approach. However, the low-temperature environment affects the operation of the used components resulting in trade-off considerations at the system design level. This work presents the design and implementation of a preamplifier for highly accurate noise figure (NF) measurements of cryogenically cooled low-noise amplifiers (LNA) in the single-digit noise temperature range. The proposed device is a 43 GHz wideband, temperature-controlled amplification system with a programmable gain of up to 60 dB. A complex three-path configurable circuit topology provides flexible high gain amplification over a broad bandwidth from 1 GHz to 44 GHz. In the scope of this work, the functionality of the preamplifier is characterized, and usability is demonstrated. The relative accuracy in the proof-of-concept scenario has increased by a factor of 80 with the utilization of the preamplifier","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Reversible-Logic based Architecture for VGGNet 基于可逆逻辑的VGGNet体系结构

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665605

Bappaditya Dey, Kasem Khalil, Ashok Kumar, M. Bayoumi

{"title":"A Reversible-Logic based Architecture for VGGNet","authors":"Bappaditya Dey, Kasem Khalil, Ashok Kumar, M. Bayoumi","doi":"10.1109/icecs53924.2021.9665605","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665605","url":null,"abstract":"Computer vision is witnessing increased usage of Convolutional-Neural-Network (CNN) deep learning architectures. Researchers have experimented with more complex architecture variants of CNN, such as VGGX, GoogleNet, and ImageNet to correlate depth of architectures, especially convolutional blocks with model accuracy. Such architectures are extensively used in complex object classification and computer vision problems such as self-driving cars, surveillance, and security systems. However, the drawbacks are high computational cost, area overhead, and excessive power dissipation since the operations involved under CNN architectures are both computationally and memory extensive. This work proposes a novel design fully reversible-logic based VGGNet architecture for low-power VLSI (Very-Large-Scale-Integration) circuit synthesis. We have implemented two architecture variants of VGGNet, as RL-VGG-16 and RL-VGG-19 using only reversible logic gates and circuits. Ideally, no information can be erased during reversible logic operations. Therefore, reversible circuits generally do not dissipate any heat. The proposed architectures have been implemented using VHDL on Altera Arria10 GX FPGA. The comparative analysis demonstrates that proposed RL-VGG-16 architecture achieves approximately an 18.08% decrease in overall power dissipation compared to the classical VGG-16 architecture. The proposed RL-VGG-19 architecture achieves approximately a 16.48% decrease in overall power dissipation compared to classical VGG-19 architecture. Both proposed approaches also have better scalability than the classical design approaches.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121392376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Simple LiFi Oximeter Monitoring system for Telehealth applications 用于远程医疗应用的简单LiFi血氧仪监测系统

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665481

M. Darweesh, Diana W. Dawoud

引用次数: 1

Forward Body Bias Technique for Low Voltage and Area Constrained LDO Design in Deep Submicron Technologies 深亚微米低电压和受限LDO设计的正向体偏置技术

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665545

Angelito A. Silverio

引用次数: 1

A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units 浮点运算单元的高性能、全利用率硬件实现

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665459

Chen Yang, Siwei Xiang, Jiaxing Wang, Liyan Liang

引用次数: 2

Simscape and LTspice models of HP ideal generic memristor based on finite closed form solution for window functions 基于窗函数有限闭形式解的HP理想通用忆阻器的Simscape和LTspice模型

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665488

S. Dautovic, N. Samardzic, A. Juhas, A. Ascoli, R. Tetzlaff

引用次数: 2