A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart SoCs

Michele Caselli, E. Tiurin, S. Stanzione, A. Boni
{"title":"A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart SoCs","authors":"Michele Caselli, E. Tiurin, S. Stanzione, A. Boni","doi":"10.1109/icecs53924.2021.9665463","DOIUrl":null,"url":null,"abstract":"This paper presents a novel architecture of a self-calibrating programmable voltage reference with nanoampere current consumption. The output voltage is generated by a programmable impedance matrix, based on MOS transistors and resistors, and periodically calibrated with a duty-cycled bandgap. In application domains where the temperature exhibits a low rate-of-change, an average current consumption of 6.5 nA is achieved, largely outperforming all the previously reported switched-capacitor or floating-gate architectures. Implemented in 55-nm CMOS technology, the reference exhibits a 0.4-to-2.5-V output voltage range, over the −20 to +80°C temperature range.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icecs53924.2021.9665463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

This paper presents a novel architecture of a self-calibrating programmable voltage reference with nanoampere current consumption. The output voltage is generated by a programmable impedance matrix, based on MOS transistors and resistors, and periodically calibrated with a duty-cycled bandgap. In application domains where the temperature exhibits a low rate-of-change, an average current consumption of 6.5 nA is achieved, largely outperforming all the previously reported switched-capacitor or floating-gate architectures. Implemented in 55-nm CMOS technology, the reference exhibits a 0.4-to-2.5-V output voltage range, over the −20 to +80°C temperature range.
一种用于智能soc的6.5 nA静态自校准可编程电压基准
本文提出了一种具有纳安培电流消耗的自校准可编程电压基准的新结构。输出电压由基于MOS晶体管和电阻的可编程阻抗矩阵产生,并定期使用占空比带隙进行校准。在温度变化率较低的应用领域,平均电流消耗为6.5 nA,大大优于之前报道的所有开关电容器或浮栅架构。该基准采用55纳米CMOS技术,在−20至+80°C的温度范围内,输出电压范围为0.4至2.5 v。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信