L. Krishna, J. B. Rao, Ayesha Sk, S. Veeramachaneni, S. Mahammad
{"title":"Energy Efficient Approximate 4:2 Compressors for Error Tolerant Applications","authors":"L. Krishna, J. B. Rao, Ayesha Sk, S. Veeramachaneni, S. Mahammad","doi":"10.1109/icecs53924.2021.9665614","DOIUrl":null,"url":null,"abstract":"In many real-life applications such as image/video processing, the error present in the output will not impact the output visual information. Approximation at the hardware level is one of the promising techniques to design energy-efficient circuits. This paper proposes an approximate 4:2 compressor design to reduce partial products in the multiplier design. The proposed approximate 4:2 compressor design consumes on an average 56% less energy compared with the existing designs from the literature, respectively. This paper proposes two variants of the approximate multiplier designs, where design1 uses only proposed approximate 4:2 compressors and multiplier design2's lower half of the multiplier is designed using proposed approximate 4:2 compressor and higher half of the multiplier is designed using existing accurate compressors to reduce the error rate and improve the output image visual quality.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icecs53924.2021.9665614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In many real-life applications such as image/video processing, the error present in the output will not impact the output visual information. Approximation at the hardware level is one of the promising techniques to design energy-efficient circuits. This paper proposes an approximate 4:2 compressor design to reduce partial products in the multiplier design. The proposed approximate 4:2 compressor design consumes on an average 56% less energy compared with the existing designs from the literature, respectively. This paper proposes two variants of the approximate multiplier designs, where design1 uses only proposed approximate 4:2 compressors and multiplier design2's lower half of the multiplier is designed using proposed approximate 4:2 compressor and higher half of the multiplier is designed using existing accurate compressors to reduce the error rate and improve the output image visual quality.