Power- and Area-optimized Neural Network IC-Design for Academic Education

Abstract

A shortage of practically skilled computer science graduates affects academia as well as the industry. Especially when it comes to hardware design and awareness about the complete digital design flow, a lack of qualified personell can hinder the progess of development teams. To address this issue, we will present the design of an integrated circuit (IC) containing a power- and area optimized neural network, enabling know-how development of the students various key skills required for hardware design. This example project, targeting bachelor and master students interested in hardware engineering and artificial intelligence, offers learning potential in various fields and enough room for creative design decisions and detailed discussions. Possible design options and improvements are discussed throughout the paper with focus on their educational aspects.