2.4 hz - 5khz通带$11.8\ \mu \ mathm {V}_{\text{RMS}}$用于脑芯片接口的噪声功率神经放大器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI:10.1109/icecs53924.2021.9665636

E. Vallicelli, A. Baschirotto, Lorenzo Stevenazzi, Luciano Rota, M. Matteis

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引用次数: 0

摘要

本文提出了一种低噪声放大器(LNA)的完整晶体管级设计，用于感应电解氧化物mos (EOMOS)脑芯片接口中的弱细胞外神经电位信号。所提出的LNA采用高效的伪电阻拓扑结构，无需任何外部校准即可合成稳定的电阻(在$\mathrm{G}\Omega$的数十阶)。LNA具有2.4 Hz的最小通带频率，分别在1 Hz - 300 Hz(局部场电位)和300 Hz - 5 kHz(动作电位)带宽下执行$7.8 \mu \mathrm{V}_{\text{RMS}}$和$8.8\ \mu \mathrm{V}_{\text{RMS}}$输入参考噪声功率。该器件功耗为$2.4 \mu \mathrm{W}$，采用28纳米CMOS技术设计。

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2.4 Hz–5 kHz Passband $11.8\ \mu \mathrm{V}_{\text{RMS}}$ Noise Power Neural Amplifier for Brain-Chip Interfaces

This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of $\mathrm{G}\Omega$ order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing $7.8 \mu \mathrm{V}_{\text{RMS}}$ and $8.8\ \mu \mathrm{V}_{\text{RMS}}$ input-referred noise power at 1 Hz – 300 Hz (Local Field Potential) and 300 Hz–5 kHz (Action Potentials) bandwidth, respectively. The device consumes $2.4 \mu \mathrm{W}$ power and has been designed in 28 nm CMOS technology.

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2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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