A 3.2-MS/s 14-Bit Extended-Range Second-Order Incremental ADC

Abstract

This paper presents a 14-bits two-stage extended-range A/D converter (ERADC), consisting of a switched-capacitor second-order incremental ADC (IADC) based on a cascade of integrators with feedforward topology as first stage, followed by a 5-bit SAR ADC as second stage. The proposed architecture, does not require any active inter-stage block for providing the residue of the IADC coarse conversion to the SAR ADC for fine conversion, thus minimizing the power consumption. This is achieved by gating the IADC feedforward paths during the last clock cycle of the IADC conversion. With a clock frequency of 80 MHz, the complete ERADC achieves in simulation a peak SNR of 86 dB and a dynamic range of 92 dB at a data rate of 3.2 MS/s (24 clock cycles per conversion).