All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS

Abstract

A concept of an all-digital ADC for technology scaling with a non-interleaved 10-GS/s VCO-based Time-A/D converter (TAD) is proposed. A complementary-ring-delay-line setup (c-RDL) simply realizes uncorrelated conditions between two TADs with a stochastic effect, resulting in being ideally scalable because of the all-digital configuration. TAD speed and resolution can inevitably be improved along with finer technologies, confirmed in a 16-nm FinFET CMOS compared to 800 to 40-nm CMOS nodes. Due to its small core area in a 16-nm CMOS, a TAD-core parallel method is compactly developed using a 4-clock-edge-shift (4CKES) type with one ring-delay-line (RDL) shared by four TAD-logic modules (TMs) with effectively modified encoders. Using post-layout simulation, the 4CKES-type-TAD with c-RDL produces 6.9-bit resolution, 3.5-ENOB and 0.0077 mm2 without any calibration with its 4-times-higher resolution compared to a single-type.