FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

Vasileios Leon, Charalampos Bezaitis, G. Lentaris, D. Soudris, D. Reisis, E. Papatheofanous, A. Kyriakos, A. Dunne, A. Samuelsson, D. Steenari
{"title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","authors":"Vasileios Leon, Charalampos Bezaitis, G. Lentaris, D. Soudris, D. Reisis, E. Papatheofanous, A. Kyriakos, A. Dunne, A. Samuelsson, D. Steenari","doi":"10.1109/icecs53924.2021.9665462","DOIUrl":null,"url":null,"abstract":"The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for onboard data processing. We examine heterogeneous computing architectures involving high-performance and low-power commercial SoCs. The current paper implements an FPGA with VPU co-processing architecture utilizing the CIF & LCD interfaces for I/O data transfers. A Kintex FPGA serves as our framing processor and heritage accelerator, while we offload novel DSP/AI functions to a Myriad2 VPU. We prototype our architecture in the lab to evaluate the interfaces, the FPGA resource utilization, the VPU computational throughput, as well as the entire data handling system's performance, via custom benchmarking.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icecs53924.2021.9665462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for onboard data processing. We examine heterogeneous computing architectures involving high-performance and low-power commercial SoCs. The current paper implements an FPGA with VPU co-processing architecture utilizing the CIF & LCD interfaces for I/O data transfers. A Kintex FPGA serves as our framing processor and heritage accelerator, while we offload novel DSP/AI functions to a Myriad2 VPU. We prototype our architecture in the lab to evaluate the interfaces, the FPGA resource utilization, the VPU computational throughput, as well as the entire data handling system's performance, via custom benchmarking.
空间应用中的FPGA和VPU协同处理:DSP/AI基准的开发和测试
在新的空间应用中,计算要求高的算法和高数据速率仪器的出现,推动了航天工业探索机载数据处理的颠覆性解决方案。我们研究了涉及高性能和低功耗商用soc的异构计算架构。本文利用CIF和LCD接口实现了一种具有VPU协同处理架构的FPGA,用于I/O数据传输。Kintex FPGA作为我们的帧处理器和传统加速器,而我们将新颖的DSP/AI功能卸载到Myriad2 VPU。我们在实验室中对我们的架构进行了原型化,通过自定义基准测试来评估接口、FPGA资源利用率、VPU计算吞吐量以及整个数据处理系统的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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