Microarchitecture Optimization for Asynchronous Stochastic Computing

Abstract

Asynchronous Stochastic Computing (ASC) is a branch of clockless Stochastic Computing methodology that encodes signals as a digital asynchronous pulse-width modulated stream that carries information within it's duty cycle and frequency. In this paper a comprehensive study into the energy and frequency optimization of Asynchronous Stochastic Computing circuits is presented. Design knobs that affect characteristics of the stream are identified and, by evaluating their sensitivity, a Pareto optimization strategy is derived. In distributed computing systems such as wearable sensors, dynamic throughput scaling is often required. The insights from the Pareto analysis, are utilized to design a scalable throughput Asynchronous Stochastic Computing Arithmetic unit, that is capable of performing Multiply-Accumulate (MAC) operations. Our simulated results in the design of the arithmetic unit prove the effectiveness of the single optimization problem through an average energy savings of 17- 32% across the two different throughput regions of operation.