2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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A 3μW, 0.65V regulator with an embedded temperature compensated voltage reference 一个3μW, 0.65V的稳压器,内置温度补偿基准电压
Fu-To Lin, Jui-Hsiang Tsai, Y. Liao
{"title":"A 3μW, 0.65V regulator with an embedded temperature compensated voltage reference","authors":"Fu-To Lin, Jui-Hsiang Tsai, Y. Liao","doi":"10.1109/SMACD.2016.7520647","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520647","url":null,"abstract":"This paper presents a 0.65-V flipped voltage follower (FVF)-based regulator with an embedded sub-1-V voltage reference. A low-pass filter is employed in the current coupling path to reduce the bias noise and improve the power supply rejection (PSR) at a low-frequency band (<;kHz). The chip is fabricated in a 0.18-μm CMOS process and occupies an active area of 0.076 mm2. The proposed FVF regulator achieves a temperature coefficient of 68-ppm/°C over 0-100 °C, with a PSR of -50 dB at 1 kHz, and can drive a 0-3 mA load current while consuming only a quiescent current of 4.5 μA at a 0.8 V supply.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SIDe-O: A toolbox for surrogate inductor design and optimization SIDe-O:代理电感设计和优化工具箱
F. Passos, E. Roca, R. Castro-López, F. Fernández
{"title":"SIDe-O: A toolbox for surrogate inductor design and optimization","authors":"F. Passos, E. Roca, R. Castro-López, F. Fernández","doi":"10.1109/SMACD.2016.7520713","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520713","url":null,"abstract":"This paper presents SIDe-O, a CAD tool developed for the design and optimization of integrated inductors based on surrogate modeling techniques. This tool provides a solution to the problem of accurately and efficiently optimizing the design of inductors. The models used present less than 1% error when compared to EM simulations while reducing the simulation time by several orders of magnitude. Additionally, the tool provides the ability to create new surrogate models for different technologies and inductor topologies. The tool also allows the creation of an S-Parameter file that accurately describes the behavior of the inductor for a given range of frequencies, which can later be used in SPICE-like simulations.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124459026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies 模拟IC布局感知尺寸方法的放置模板的动态探索
R. Martins, A. Canelas, N. Lourenço, N. Horta
{"title":"On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies","authors":"R. Martins, A. Canelas, N. Lourenço, N. Horta","doi":"10.1109/SMACD.2016.7520731","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520731","url":null,"abstract":"In this paper, a methodology for automatic generation of placement templates for analog integrated circuit (IC) design is proposed and targeted to state-of-the-art layout-aware circuit-sizing flows. The multi-objective optimization (MOO)-based placement templates generator (PTG) inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, that fit the current state of the optimization process and are used within the layout-aware methodology to generate the floorplan of the following tentative solutions. This innovative methodology combines the advantages of previous template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of Pareto set. Moreover, as the PTG runs in parallel with the layout-aware loop, it has no impact on the layout-aware execution time. Experimental results present solutions with 47% less area when compared to a multi-template layout-aware approach.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121776234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analysis of Phase-Locked Loops using the Best Linear Approximation 用最佳线性逼近分析锁相环
D. Peumans, A. Cooman, G. Vandersteen
{"title":"Analysis of Phase-Locked Loops using the Best Linear Approximation","authors":"D. Peumans, A. Cooman, G. Vandersteen","doi":"10.1109/SMACD.2016.7520652","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520652","url":null,"abstract":"During the early design stage of Phase-Locked Loops, linear models are thoroughly used to analyse the steady-state behaviour. In reality, the envisioned linear performance is degraded due to nonlinearities present in the actual implementation. Lately, a nonlinear modelling technique based on the Best Linear Approximation has been developed which allows to verify the validity of this linear model and, in addition, permits to characterise the nonlinear distortions present in the system. Incorporating this Best Linear Approximation in the design stage allows to intuitively analyse the nonlinear behaviour of the Phase-Locked Loop.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131318213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis-based methodology for high-speed multi-modulus divider 高速多模分频器的综合方法
Dimo Martev, S. Hampel, Ulf Schlichtmann
{"title":"Synthesis-based methodology for high-speed multi-modulus divider","authors":"Dimo Martev, S. Hampel, Ulf Schlichtmann","doi":"10.1109/SMACD.2016.7520727","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520727","url":null,"abstract":"This paper presents the design flow for a radio frequency multi-modulus divider, located in a digital phase-locked loop, using a standard-cell library in 28 nm CMOS technology. The flow is based on VLSI tools for synthesis and automated place and route. The resulting design has a technology-independent fully behavioral description that allows fast translation to the next technology node. Being synthesizable, the divider is fully generic, VHDL as well as constraints, and can easily be modified and adapted for various applications and requirements. Pre-silicon verification based on sign-off static timing analysis shows operability of the design to up to 4.3GHz.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114800239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of semiconductors on the performance of Wireless Power Transfer Systems 半导体对无线电力传输系统性能的影响
G. D. Capua, N. Femia, G. Lisi, G. Petrone
{"title":"Impact of semiconductors on the performance of Wireless Power Transfer Systems","authors":"G. D. Capua, N. Femia, G. Lisi, G. Petrone","doi":"10.1109/SMACD.2016.7520728","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520728","url":null,"abstract":"This paper discusses the losses analysis of low power high-frequency Wireless Power Transfer Systems (WPTSs). The global influence of semiconductor devices parameters on the overall WPTS performances is numerically determined, by solving the non linear equations of the system discussed herein. Experimental measurements on a 2W@6.78MHz WPTS for wearable applications demonstrate the validity of the analysis.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122445507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis 一种有效的方法来表征静态时序分析的TSPC触发器设置时间
Sayyaparaju Sagar Varma, A. Sharma, B. Anand
{"title":"An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis","authors":"Sayyaparaju Sagar Varma, A. Sharma, B. Anand","doi":"10.1109/SMACD.2016.7520724","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520724","url":null,"abstract":"Static timing analysis (STA), which is a part of design automation requires the generation and storage of delay values for combinational standard cells and the setup and hold time values for sequential cells at numerous corners in the form of a Look Up Table (LUT). This paper proposes a novel approach for LUT generation of sequential standard cells by developing a model for the setup time. The model uses the input data transition time (TR) and the output capacitance (CL) as its variables with two fitting parameters. The model's validity is verified through simulations in Cadence Virtuoso and using this model, it is shown that it reduces the number of simulations needed for the generation of a 6 × 6 LUT by 91.67%, while having an average percentage error of 2.28%. Also, the dependence of the fitting parameters on the sizing of the devices and their relation with process, voltage and temperature variations is shown and verified.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123988115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel energy-efficient self-correcting methodology employing INWE 采用INWE的新型节能自校正方法
C. I. Kumar, A. Sharma, S. Miryala, B. Anand
{"title":"A novel energy-efficient self-correcting methodology employing INWE","authors":"C. I. Kumar, A. Sharma, S. Miryala, B. Anand","doi":"10.1109/SMACD.2016.7520744","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520744","url":null,"abstract":"Operating VLSI circuits at near/sub-threshold region is emerging as the most important technique for low power applications. However, due to the increasing variability in sub-threshold regime, system performance and yield is at stake. Therefore, improved circuit techniques are needed with low power overhead which can essentially improve the yield. This paper presents a timing error Self Correcting Flip-Flop (SCFF) operating at near threshold voltage. The proposed SCFF automatically corrects timing faults in sequential elements and datapaths, thereby reducing performance degradation due to variations and improves yield. The proposed technique uses Inverse Narrow Width effect (INWE) for performance optimization. The proposed methodology is evaluated by considering few custom circuits along the data-path. The simulation results show that the proposed SCFF design achieves better yield ratio for a given frequency specification, ~0.33 at 0.4v and ~0.32 at 0.35v supply voltage against existing error detection and correction methods.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130747703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient and automated generation of multidimensional design curves for coupled-resonator filters using system identification and metamodels 利用系统辨识和元模型高效、自动化地生成耦合谐振器滤波器的多维设计曲线
Matthias Caenepeel, F. Ferranti, Y. Rolain
{"title":"Efficient and automated generation of multidimensional design curves for coupled-resonator filters using system identification and metamodels","authors":"Matthias Caenepeel, F. Ferranti, Y. Rolain","doi":"10.1109/SMACD.2016.7520717","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520717","url":null,"abstract":"The design of coupled-resonator microwave band-pass filter is very often based on the physical implementation of a coupling matrix by correctly dimensioning the filter (geometrical) design parameters. An initial dimensioning is carried out using the design curves that describe the inter-resonator coupling parameter and external quality factor as a function of (geometrical) design parameters of a coupled-resonator pair and a single loaded resonator, respectively. These curves are usually generated using electromagnetic (EM) simulations. In order to minimize the number of EM simulations, these curves often consider only a single design parameter, while in reality several design parameters influence the inter-resonator coupling parameter and external quality factor. In this paper, a metamodeling method is used to generate multidimensional design curves with a minimal number of EM simulations, while maintaining a good accuracy. Moreover, their generation process is fully automated. The automated generation of multidimensional design curves for a coupled hairpin resonator filter validates the proposed method.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131567731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Efficient signature selection tool for sense & react systems 有效的签名选择工具,用于感知和反应系统
Engin Afacan, Günhan Dündar, A. E. Pusane, Faik Piaskaya, M. B. Yelten
{"title":"Efficient signature selection tool for sense & react systems","authors":"Engin Afacan, Günhan Dündar, A. E. Pusane, Faik Piaskaya, M. B. Yelten","doi":"10.1109/SMACD.2016.7520714","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520714","url":null,"abstract":"Reconfigurable circuit design has become very important in the last decade for increasing the lifetime of CMOS circuits in deep sub-micron technologies. Sense & React approach is one of the reconfigurable design approaches, where degradation in a circuit performance is detected via sensor circuitry and a pre-established recovery operation is applied to circuit. However, sense operations are quite problematic since direct measurement of the degradation in circuit performance is highly complicated. Therefore, indirect measurements are preferred, in which one or more relevant circuit variables, which are called signatures, are selected out of measurable circuit quantities. Conventionally, the designer selects the signatures by performing an iterative search and evaluation on aging simulation results, and no such procedure has been defined in the literature yet. This paper proposes an efficient selection methodology and tool for determining efficient signatures for sense operation.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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