Synthesis-based methodology for high-speed multi-modulus divider

This paper presents the design flow for a radio frequency multi-modulus divider, located in a digital phase-locked loop, using a standard-cell library in 28 nm CMOS technology. The flow is based on VLSI tools for synthesis and automated place and route. The resulting design has a technology-independent fully behavioral description that allows fast translation to the next technology node. Being synthesizable, the divider is fully generic, VHDL as well as constraints, and can easily be modified and adapted for various applications and requirements. Pre-silicon verification based on sign-off static timing analysis shows operability of the design to up to 4.3GHz.