I. Elfergani, A. Hussaini, Jonathan Rodriguez, R. Abd‐Alhameed
{"title":"Miniaturized dual-band balanced antenna for LTE using meander lines","authors":"I. Elfergani, A. Hussaini, Jonathan Rodriguez, R. Abd‐Alhameed","doi":"10.1109/SMACD.2016.7520733","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520733","url":null,"abstract":"A new compact dual-band balanced antenna is proposed with meandered lines operating in the LTE bands of 700/2600MHz. It has a compact size with the overall dimensioning of 54×18× 8 mm3, in which can be simply concealed within mobile handsets. Techniques such as meandered lines are used in order to accomplish a well-matching and size reduction of antenna. The meander lines were printed on FR4 substrate with relative permittivity of 4.4 and dielectric loss tangent of 0.0017 with a thickness of 1.6 mm. The results of the present design structure were checked in terms of reflection coefficient, operational bandwidth, current surface, and radiation pattern characteristics. The results have shown that the proposed design can be an attractive candidate for use in mobile handset.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116712378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs","authors":"P. Bahubalindruni, J. Goes, P. Barquinha","doi":"10.1109/SMACD.2016.7520732","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520732","url":null,"abstract":"This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jesus Lopez-Arredondo, E. Tlelo-Cuautle, F. V. Fernández
{"title":"Optimization of LDO voltage regulators by NSGA-II","authors":"Jesus Lopez-Arredondo, E. Tlelo-Cuautle, F. V. Fernández","doi":"10.1109/SMACD.2016.7520743","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520743","url":null,"abstract":"Two different low-dropout (LDO) voltage regulators are optimized by applying the Non-Dominated Sorting Genetic Algorithm II (NSGA-II). First, from a sensitivity analysis a set of design variables are selected to establish a reduced chromosome for performing multi-objective optimization by NSGA-II. The computed sensitivities are used to reduce the search spaces for the design variables included into the chromosome, so that the optimization process is accelerated. Second, a comparison between traditional and optimization-based design approaches is shown by considering 2 figures of merit (FoM). Finally, we list the results for optimizing 2 LDO voltage regulators for the 2 FoMs, and provide optimized sizes that are compared to traditional design.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Canelas, R. Martins, R. Póvoa, N. Lourenço, N. Horta
{"title":"Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations","authors":"A. Canelas, R. Martins, R. Póvoa, N. Lourenço, N. Horta","doi":"10.1109/SMACD.2016.7520729","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520729","url":null,"abstract":"This paper presents an efficient yield optimization approach using k-means clustering algorithm to reduce Monte Carlo (MC) simulations. This approach uses a commercial electrical simulator and PDK models for evaluation purposes. The method was integrated in an analog IC design flow that includes the AIDA-C circuit sizing optimization tool. The proposed yield estimation technique reduces the number of required MC simulations during the optimization process. The simulated solutions are the most likely to populate the Pareto optimal front and result from a selection process based on a modified k-means algorithm. The proposed approach leads 75% reduction in the total number of the MC simulations for the presented case study.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Benjamin Prautsch, Uwe Eichler, S. Rao, Bjorn Zeugmann, A. Puppala, T. Reich, J. Lienig
{"title":"IIP framework: A tool for reuse-centric analog circuit design","authors":"Benjamin Prautsch, Uwe Eichler, S. Rao, Bjorn Zeugmann, A. Puppala, T. Reich, J. Lienig","doi":"10.1109/SMACD.2016.7520725","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520725","url":null,"abstract":"Current design of analog integrated circuits is still a time-consuming manual process resulting in static analog blocks which can hardly be reused. In order to address this problem, a new framework to ease reuse-centric bottom-up design of analog integrated circuits is introduced. Our IIP Framework (IIP: Intelligent Intellectual Property) enables the development of highly technology-independent analog circuit generators applicable in multiple design environments. IIP Generators are parameterizable descriptions of each view of an analog block, i.e., layout, schematic, and symbol. They allow the adaptation of complex layouts within seconds to minutes in order to incorporate hardly estimable parasitics and further considerations into the design flow. Due to the abstract generator description, valid design data is created for very different technologies such as 28 nm and 180 nm bulk CMOS, 28 nm FD-SOI, and others. The design experiment shows that procedural generators can be an effective tool for the efficient design of analog integrated circuits.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"73 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113992509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Piccinni, G. Avitabile, G. Coviello, C. Talarico
{"title":"Distributed amplifier design for UWB positioning systems using the gm over id methodology","authors":"G. Piccinni, G. Avitabile, G. Coviello, C. Talarico","doi":"10.1109/SMACD.2016.7520739","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520739","url":null,"abstract":"In this paper we exploit the gm over ID methodology to optimize the design of a four stage conventional Distributed Amplifier (DA) for an Ultra-Wide Band positioning system. The W/L ratio and the DC-biasing of the amplifier's transistors are determined according to the gm over ID methodology by using a series of lookup tables generated starting from the model of the devices. The DA was designed using the IHP 0.13 μm SiGe process and provides a 14 dB gain over a bandwidth of 10.6 GHz. The input/output return loss of the amplifier is lower than -17 dB over the entire bandwidth, with an average noise figure of 1.95 dB and a 26 mW DC-power consumption.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131749835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiresolution modeling of cavity resonators in microwave systems","authors":"Brigita Sziová, S. Nagy, A. Fehér, J. Pipek","doi":"10.1109/SMACD.2016.7520651","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520651","url":null,"abstract":"Multiresolution analysis or wavelet analysis provides a toolbox not only for signal processing, but also for synthesis of complex systems. Wavelets can be used for modeling complex parts of microwave circuits, such as cavity resonators. The differential equations describing the physical behavior of the device can be discretized using multiple resolutions simultaneously, i.e., high resolutions, where the details of the geometry demand it, and low resolutions, where the geometry is smooth. Using wavelet analysis offers the possibility of systematic and adaptive refinement, where the result is not sufficiently precise. Our method gives an approximation for the error of the solution in order to make it possible to decide, whether refinements are necessary.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133135367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Towards the simulatable specification of a highly customisable SystemC AMS alternator model in its multi-domain environment","authors":"V. Tran, P. Tisserand, F. Pêcheux, A. Pinna","doi":"10.1109/SMACD.2016.7520716","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520716","url":null,"abstract":"This paper presents a refinable and customisable alternator model with its heterogeneous environment, all implemented in SystemC and SystemC-AMS. The virtual prototype can be configured easily, and the embedded software can be changed at any time. Experience has shown that the overall development time can be reduced. Indeed, with a high-level configurable description of the environment and a refinable synchronous machine system model, electronic designers can easily evaluate performances according to architecture exploration.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114946181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A specialized time-step control strategy for fast simulation of switching power electronic circuits","authors":"J. Wilhelm, W. Renhart","doi":"10.1109/SMACD.2016.7520736","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520736","url":null,"abstract":"Simulation times of electric circuits containing switching power supplies not only depend on the algorithms used for solving the network equations but also on the choice of the time-step-control strategy. While generic simulation packages use the estimated truncation error to find the optimum time step, in this work a more specialized approach was followed. After studying the analytic solution and the simulation results of a circuit utilizing a pulse-with-modulation scheme it was found, that the switching intervals form adequate time-steps. To prove this, a basic simulation software was implemented and several simulations were conducted. Finally, the simulation accuracy was improved by introducing additional time-steps and impact on the convergence speed and memory consumption was studied.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125567729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Verilog-A model of a charge sensitive amplifier for a HV-CMOS pixel sensor","authors":"R. Casanova, S. Grinstein","doi":"10.1109/SMACD.2016.7520748","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520748","url":null,"abstract":"The use of hybrid pixel detectors in High Energy Physics (HEP) have allowed particle tracking reconstruction with an unprecedented precision. These detectors are expensive to assembly and the bump size limits the minimum pixel size. In order to overcome those limitations full monolithic pixels are being investigated. The idea is to integrate into the same chip the sensor matrix and the readout electronics. Simultaneously, new methods for measuring the energy of the detected particles with higher precision that those achievable by using the Time Over Threshold (TOT) technique are under study. This paper presents a behavioral model of the preamplifier stage of a pixel readout channel written in Verilog-A. The purpose of this model is to allow studying different solutions for measuring the energy with higher precision without the need to design the readout channel at transistor level. The presented model is very simple and written as a function of the main parameters of the pre-amplifier stage, that is, open loop gain, bandwidth, coupling capacitor, and feedback capacitor.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}