{"title":"In-system IGBT power loss behavioral modeling","authors":"N. Femia, M. Migliaro, C. Pastore, Davide Toledo","doi":"10.1109/SMACD.2016.7520723","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520723","url":null,"abstract":"In high-power-density power electronics applications, it is important to predict the power losses of semiconductor devices in order to maximize global system efficiency and avoid thermal damages of the components. When different effects influence the power losses, some of which difficult to be physically modeled, it is worthwhile to use empirical laws obtained starting from experimental data, like the Steinmetz's equation widely used for inductors' magnetic core losses prediction. This paper discusses a method to find empirical power loss models by using Genetic Programming (GP). In particular, the GP approach has been applied to identify power losses in Insulated Gate Bipolar Transistors for Induction Cooking application. A loss model has been obtained using an experimental training set, and the result has been successively validated.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116886545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Bahubalindruni, V. Tavares, P. Barquinha, R. Martins, E. Fortunato
{"title":"Basic analog and digital circuits with a-IGZO TFTs","authors":"P. Bahubalindruni, V. Tavares, P. Barquinha, R. Martins, E. Fortunato","doi":"10.1109/SMACD.2016.7520741","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520741","url":null,"abstract":"This paper presents the characterization of fundamental analog and digital circuits with a-IGZO TFTs from measurements performed at normal ambient. The fundamental blocks considered in this work include digital logic gates, a low-power single stage high-gain amplifier with capcacitive bootstrapping and a level shifter/buffer. These circuits are important functional blocks in analog/Mixed signal IC design with oxide TFTs. Being fabricated at low temperature (<; 200 °C), they can find potential applications in low-cost large-area flexible systems.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"24 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113935422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Engin Afacan, Günhan Dündar, A. E. Pusane, I. F. Baskaya
{"title":"Semi-empirical aging model development via accelerated aging test","authors":"Engin Afacan, Günhan Dündar, A. E. Pusane, I. F. Baskaya","doi":"10.1109/SMACD.2016.7520720","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520720","url":null,"abstract":"Modelling of the degradation mechanisms has a crucial role during the aging analysis, which determines the accuracy of the lifetime estimation. Conventionally, analytical and semi-empirical models are utilized during the aging analysis. Analytical models employ deterministic equations during the degradation calculation and they can be scaled for different technology nodes; hence providing flexibility. However, scaling errors and approximations during the model development may degrade the accuracy. On the other hand, semi-empirical models are generated via accelerated aging test (AAT) performed on the silicon, which often promise more reliable results for a given technology. This paper comprehensively examines the semi-empirical modelling process from test chip design to AAT experiments.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128747027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Axel Hald, Johannes Seelhorst, M. Reimann, J. Scheible, J. Lienig
{"title":"A novel polygon-based circuit extraction algorithm for full custom designed MEMS sensors","authors":"Axel Hald, Johannes Seelhorst, M. Reimann, J. Scheible, J. Lienig","doi":"10.1109/SMACD.2016.7520719","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520719","url":null,"abstract":"In contrast to IC design, MEMS design still lacks sophisticated component libraries. Therefore, the physical design of MEMS sensors is mostly done by simply drawing polygons. Hence, the sensor structure is only given as plain graphic data which hinders the identification and investigation of topology elements such as spring, anchor, mass and electrodes. In order to solve this problem, we present a rule-based recognition algorithm which identifies the architecture and the topology elements of a MEMS sensor. In addition to graphic data, the algorithm makes use of only a few marking layers, as well as net and technology information. Our approach enables RC-extraction with commercial field solvers and a subsequent synthesis of the sensor circuit. The mapping of the extracted RC-values to the topology elements of the sensor enables a detailed analysis and optimization of actual MEMS sensors.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130045702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new table based modelling of 28nm fully depleted silicon-on insulator (FDSOI)","authors":"Abdelgader M. Abdalla, Jonathan Rodriguez","doi":"10.1109/SMACD.2016.7520746","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520746","url":null,"abstract":"In this work, a multivariate interpolation lookup tables (LUTs) model for nanometer CMOS transistors is presented. A novel lookup-table (LUT) method, which is based on a multivariate Neville's algorithm for the current-voltage (I-V) and Capacitance-voltage (C-V) characteristics of a transistor, is proposed for the simulation of MOS transistor circuits. The simulation speed is noted to be significantly enhanced with sufficient accuracy via a dynamic programming procedure with the implementation of the proposed approach compared to the current state of the art models. Simulation results are implemented in a 28-nm fully depleted SOI technology (FDSOI). Compared to simulations with both the BSIMSOI model and the Lagrange interpolation lookup table, the computation time of the proposed approach can be reduced by 8.X and beyond in transient analysis.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133645872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Moving beyond traditional electronic design automation: Data-driven design of analog circuits","authors":"Xiaowei Liu, A. Doboli","doi":"10.1109/SMACD.2016.7520726","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520726","url":null,"abstract":"Understanding the relation between the characteristics of the referenced ideas (as expressed by the cited papers) and the expected impact of a new design (as measured by the received citation count) is important in maximizing the outcomes of the spent design effort, time, and resources. This paper presents a new methodology and the related metrics and procedures to analyze this connection. The approach was utilized to study the distinguishing features of highly-cited papers on switched capacitor filter design. A set of pattern specific to these papers are discussed in the paper.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"23 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Özlem Karaca, Jérôme Kirscher, A. Laroche, Andreas Tributsch, L. Maurer, G. Pelz
{"title":"Fault grouping for fault injection based simulation of AMS circuits in the context of functional safety","authors":"Özlem Karaca, Jérôme Kirscher, A. Laroche, Andreas Tributsch, L. Maurer, G. Pelz","doi":"10.1109/SMACD.2016.7520721","DOIUrl":"https://doi.org/10.1109/SMACD.2016.7520721","url":null,"abstract":"The fault injection technique is utilized for simulation-based verification of safety-related analog and mixed-signal (AMS) circuits for compliance with safety requirements in the presence of hardware faults. Exhaustive fault simulation is very time consuming with respect to the number of faults to simulate at circuit level. For efficient simulation-based verification, a fault grouping approach is proposed to reduce the number of faults to simulate without missing out potentially safety-critical faults. The fault grouping approach is based on component-level fault simulation, hierarchical clustering and internal cluster validation. The effectiveness is investigated on a component extracted from an automotive safety-related System on a Chip.","PeriodicalId":441203,"journal":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128108505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}