A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs

Abstract

This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.