一种用于sar辅助管路adc的高增益、高速参数化残差放大器

2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2016-06-27 DOI:10.1109/SMACD.2016.7520732

P. Bahubalindruni, J. Goes, P. Barquinha

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引用次数: 2

摘要

提出了一种用于两级sar辅助管路ADC的高速高增益动态剩余放大器。为了满足ENOB≥10.5位模数转换器对剩余放大器的工业要求，在剩余放大器中加入参数放大技术以提高增益。仿真结果表明，在标准65纳米CMOS技术中，当VDD为1.2 V, CL为150 fF时，工作频率为1.75 GHz，电路增益为22.05 dB，功耗为0.31 mW。

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A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs

This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.

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2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

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