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SiGe BiCMOS Technology: An IC Design Platform for Extreme Environment Electronics Applications SiGe BiCMOS技术:用于极端环境电子应用的集成电路设计平台
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369883
J. Cressler
{"title":"SiGe BiCMOS Technology: An IC Design Platform for Extreme Environment Electronics Applications","authors":"J. Cressler","doi":"10.1109/RELPHY.2007.369883","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369883","url":null,"abstract":"The drivers in the extreme environment electronics community are beginning to perk up their ears to the possibilities of using SiGe technology, especially for space electronics applications. The present NASA-funded project, \"SiGe integrated electronics for extreme environments,\" which is aimed at enabling more effective lunar exploration, represents a 'first' of sorts - a chance to develop the requisite SiGe infrastructure; from technology, to characterization tools, to modeling, to circuit design, to packaging, to reliability, to functional sub-systems, needed to support the development and eventual insertion of SiGe into emerging extreme environment venues. The authors are excited about our progress, and firmly believe that the greater electronics community can and should leverage this effort for a wide variety of their applications. Ensuring adequate reliability for SiGe technologies in these new application venues will require more effort from the reliability community. Initial results look very promising indeed.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121424442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Erratic Bit Errors in Latches 锁存器中不稳定的位错误
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369931
P. Relangi, S. Mitra
{"title":"Erratic Bit Errors in Latches","authors":"P. Relangi, S. Mitra","doi":"10.1109/RELPHY.2007.369931","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369931","url":null,"abstract":"Erratic bit errors are caused by erratic shifts in Vmin, the minimum supply voltage at which a design can correctly operate, due to trapping/detrapping of electrons and holes in the gate oxide. The authors study the effects of erratic bit errors in latches through SPICE simulation using the gate-to-source resistive short model. The authors demonstrate that a latch structure using a redundant latch and a C-element corrects most latch erratic bit errors and significantly reduces their impact. This structure enables chip-level power reduction by enabling chip operation at low voltage through erratic bit error correction in latches. This structure can also correct radiation-induced soft errors and is referred to as BISER or built-in-soft-error resilience structure.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116640313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On The Interaction of ESD, NBTI and HCI in 65nm Technology 65纳米工艺中ESD、NBTI和HCI的相互作用研究
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369862
R. Mishra, S. Mitra, R. Gauthier, D. Ioannou, D. Kontos, K. Chatty, C. Seguin, R. Halbach
{"title":"On The Interaction of ESD, NBTI and HCI in 65nm Technology","authors":"R. Mishra, S. Mitra, R. Gauthier, D. Ioannou, D. Kontos, K. Chatty, C. Seguin, R. Halbach","doi":"10.1109/RELPHY.2007.369862","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369862","url":null,"abstract":"A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFET devices is presented for a state-of-the-art 65nm bulk technology. ESD behavior of thin and thick oxide devices are shown to have opposite channel length dependence. The study of NBTI-ESD interaction on thin oxides devices shows that non-destructive ESD pre-stressing worsens the NBTI degradation. On the other hand NBTI pre-stressed thick oxide devices show high on-resistance during ESD characterization. It is shown that in thin oxide long channel length devices at high temperature pure NBTI is the worst case degradation mode whereas in short channel length devices combined \"HC-NBTI\" degradation dominates. Furthermore, we observed that while a SBLK PFET is HC stressed at high temperature then NBTI also takes place simultaneously, resulting in \"HC-NBTI\" co-activation, which is found to be channel length dependent. Finally, we have shown that HC degradation is worse at high temperature than at room temperatures due to this NBTI co-activation.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114162728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer 采用部分绝缘层的块体finet可靠性研究
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369919
J. Park, Jong-Man Park, S. Sohn, Jun-Bum Lee, C. Jeon, Sang-yeon Han, S. Yamada, Wouns Yang, Yonghan Roll, Donggun Park
{"title":"Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer","authors":"J. Park, Jong-Man Park, S. Sohn, Jun-Bum Lee, C. Jeon, Sang-yeon Han, S. Yamada, Wouns Yang, Yonghan Roll, Donggun Park","doi":"10.1109/RELPHY.2007.369919","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369919","url":null,"abstract":"This paper presents a detailed analysis of the reliability characteristics of partially-insulated FinFETs (PI-FinFETs) where a new source/drain structure was adapted using a pad-polysilicon side contact (PSC). The PSC structure shows excellent improvements in device performances mainly due to the increment of the contact area by using lateral faces of FinFETs. The hot carrier degradation characteristics are also improved in comparison with a conventional source/drain structure having planar contact. This is due to an advantageous impact ionization position. By applying PSC structure to Pi-FinFETs, an optimized source/drain structure of PI-FinFETs can be obtained with its own advantages.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125411929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Role of Oxide/Nitride Interface Traps on the Nanocrystal Memory Characteristics 氧化物/氮化物界面陷阱对纳米晶体记忆特性的影响
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369999
A. Gasperin, A. Cester, N. Wrachien, A. Paccagnella, C. Gerardi, V. Ancarani
{"title":"Role of Oxide/Nitride Interface Traps on the Nanocrystal Memory Characteristics","authors":"A. Gasperin, A. Cester, N. Wrachien, A. Paccagnella, C. Gerardi, V. Ancarani","doi":"10.1109/RELPHY.2007.369999","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369999","url":null,"abstract":"In this work we are addressing the threshold voltage instability observed in non volatile nanocrystal memories (NCMs) during the retention experiments under constant applied bias. Such instability derives from the charge motion at the oxide/nitride interface traps of the oxide/nitride/oxide stack employed as control dielectric. We also investigated the impact of temperature on the cell retention properties, showing important and original results that could be attributed to the structure of the control dielectric stack.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Investigation of hot carrier effects in n-MOSFETs thick oxide with HfSiON and SiON gate dielectrics 采用HfSiON和SiON栅介质的n- mosfet中热载子效应的研究
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369981
K. Nam, S. Lee, D. Kim, S. Hyun, J. Kim, I. Jeon, S.B. Kang, S. Choi, U. Chung, J. Moon
{"title":"Investigation of hot carrier effects in n-MOSFETs thick oxide with HfSiON and SiON gate dielectrics","authors":"K. Nam, S. Lee, D. Kim, S. Hyun, J. Kim, I. Jeon, S.B. Kang, S. Choi, U. Chung, J. Moon","doi":"10.1109/RELPHY.2007.369981","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369981","url":null,"abstract":"This paper reports the reliability characteristics of poly gated n-MOSFETs with HfSiON and SiON gate dielectrics in both thin and thick oxide of dual gate oxide scheme. Hot carrier stress (HCS) at Isub, max condition on thick oxide is found to be the most critical part among the various reliability concerns. Regardless of gate dielectric and gate oxide thickness, the degradation behavior of the condition of Isub, max and Vg=Vd HCS is mainly SS increase and Vth shift, respectively. Therefore, for precise evaluation of the device reliability, it is necessary that HC immunity at Isub, max stress should be checked in thick oxide transistor below 50 nm design rule era.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126564360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory 横向电荷扩散对TANOS (TaN/AlO/SiN/Oxide/Si) NAND闪存可靠性的影响
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369887
Chang-seok Kang, Jungdal Choi, J. Sim, Changhyun Lee, Yoocheol Shin, Jintaek Park, Jongsun Sel, S. Jeon, Young-woo Park, Kinam Kim
{"title":"Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory","authors":"Chang-seok Kang, Jungdal Choi, J. Sim, Changhyun Lee, Yoocheol Shin, Jintaek Park, Jongsun Sel, S. Jeon, Young-woo Park, Kinam Kim","doi":"10.1109/RELPHY.2007.369887","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369887","url":null,"abstract":"It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the trap layers between gate lines suggests that the lateral charge spreading via trap layers from the programmed cells to the adjacent erased cells contributes to the charge loss of the TANOS cells.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"351 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Phase Variation Mapping, a Dynamic Laser Stimulation Technique with Picosecond Timing Resolution 相位变化映射，一种具有皮秒定时分辨率的动态激光刺激技术
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369947
K. Sanchez, P. Perdu, F. Beaudoin
{"title":"Phase Variation Mapping, a Dynamic Laser Stimulation Technique with Picosecond Timing Resolution","authors":"K. Sanchez, P. Perdu, F. Beaudoin","doi":"10.1109/RELPHY.2007.369947","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369947","url":null,"abstract":"Timing issues in modern CMOS technology can be very difficult to localize, especially when circuits are sensitive to timing variation in the picosecond range. Very powerful time resolved emission (TRE) tools are limited to bandwidths of sim;52 ps and can be SNR limited. Dynamic laser stimulation (DLS) identifies circuit's marginal regions by slightly perturbing local timing. It has the unique ability to induce timing perturbations proportional to the laser beam power. Therefore, timing perturbation can be made sufficiently small (i.e. in the picosecond range or less) not to modify the overall device behavior. Laser induced timing perturbation can speed-up or slow down transitions either from 1 to 0 (VDD to VSS) or from 0 to 1 (VSS to VDD). Knowledge of the physics behind those effects will help the designer or failure analyst to resolve timing issues. Unfortunately, timing perturbation measurements are often difficult to perform with suitable accuracy. This paper presents a new technique, phase variation mapping (PVM), which overcomes measurement accuracy issues. The measurement is based on a phase sensitive detector which provides an analog output representation of the laser induced timing variation. PVM belongs to a broader class of variation mappings techniques (which we refer to as `xVM') aimed at solving a variety of marginality-related IC issues","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131581476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design for Manufacturability and its Role in Enhancing Stress Migration Reliability of Porous Ultra Low-k Copper Interconnects 可制造性设计及其在提高多孔超低k铜互连应力迁移可靠性中的作用
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369882
Y. K. Lim, K. Pey, P. Lee, Y. Lee, N. Kamat, J.B. Tan, T. Fu, L. Hsia
{"title":"Design for Manufacturability and its Role in Enhancing Stress Migration Reliability of Porous Ultra Low-k Copper Interconnects","authors":"Y. K. Lim, K. Pey, P. Lee, Y. Lee, N. Kamat, J.B. Tan, T. Fu, L. Hsia","doi":"10.1109/RELPHY.2007.369882","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369882","url":null,"abstract":"The integration of copper (Cu) and low-k dielectrics has posed challenges for stress migration (SM) reliability. Besides process tuning, design for manufacturability (DFM) approach is proposed to suppress stress-induced void failures. In this paper, a three-dimensional (3D) finite element analysis (FEA) simulation model was used to identify the main mechanisms of several key processes and design approaches responsible for SM reliability improvement reported in the literature. On the basis of understanding the critical parameters and design/structural weak points affecting SM reliability, DFM is proposed to enhance the SM reliability of future nanoscale technologies employing porous ultra low-k dielectrics. The study illustrates the importance of process and design interactions to make porous ultra low-k Cu interconnects more resilient to SM degradation for future CMOS technologies.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124631993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Leakage Suppression of Low Voltage Transient Voltage Suppressor 低压瞬态电压抑制器的泄漏抑制
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual Pub Date : 2007-04-01 DOI: 10.1109/RELPHY.2007.369966
Sheng-Huei Dai, Hai-ning Wang, M. Chiang, C. Lin, Y. King
{"title":"Leakage Suppression of Low Voltage Transient Voltage Suppressor","authors":"Sheng-Huei Dai, Hai-ning Wang, M. Chiang, C. Lin, Y. King","doi":"10.1109/RELPHY.2007.369966","DOIUrl":"https://doi.org/10.1109/RELPHY.2007.369966","url":null,"abstract":"In this work, both the blanket implanted and LOCOS diodes have obvious effect on reducing the electric field at junction edge. The leakage at low biased voltage is lowered. The LOCOS diode further enhances sharpness of I-V characteristics. Besides, no extra lithography process is needed for the process of the LOCOS diodes. The LOCOS diodes would be a simple, low cost, and effective method for improving the performance of low voltage transient suppressor","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124737654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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