Erratic Bit Errors in Latches

Abstract

Erratic bit errors are caused by erratic shifts in Vmin, the minimum supply voltage at which a design can correctly operate, due to trapping/detrapping of electrons and holes in the gate oxide. The authors study the effects of erratic bit errors in latches through SPICE simulation using the gate-to-source resistive short model. The authors demonstrate that a latch structure using a redundant latch and a C-element corrects most latch erratic bit errors and significantly reduces their impact. This structure enables chip-level power reduction by enabling chip operation at low voltage through erratic bit error correction in latches. This structure can also correct radiation-induced soft errors and is referred to as BISER or built-in-soft-error resilience structure.