可制造性设计及其在提高多孔超低k铜互连应力迁移可靠性中的作用

Y. K. Lim, K. Pey, P. Lee, Y. Lee, N. Kamat, J.B. Tan, T. Fu, L. Hsia
{"title":"可制造性设计及其在提高多孔超低k铜互连应力迁移可靠性中的作用","authors":"Y. K. Lim, K. Pey, P. Lee, Y. Lee, N. Kamat, J.B. Tan, T. Fu, L. Hsia","doi":"10.1109/RELPHY.2007.369882","DOIUrl":null,"url":null,"abstract":"The integration of copper (Cu) and low-k dielectrics has posed challenges for stress migration (SM) reliability. Besides process tuning, design for manufacturability (DFM) approach is proposed to suppress stress-induced void failures. In this paper, a three-dimensional (3D) finite element analysis (FEA) simulation model was used to identify the main mechanisms of several key processes and design approaches responsible for SM reliability improvement reported in the literature. On the basis of understanding the critical parameters and design/structural weak points affecting SM reliability, DFM is proposed to enhance the SM reliability of future nanoscale technologies employing porous ultra low-k dielectrics. The study illustrates the importance of process and design interactions to make porous ultra low-k Cu interconnects more resilient to SM degradation for future CMOS technologies.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design for Manufacturability and its Role in Enhancing Stress Migration Reliability of Porous Ultra Low-k Copper Interconnects\",\"authors\":\"Y. K. Lim, K. Pey, P. Lee, Y. Lee, N. Kamat, J.B. Tan, T. Fu, L. Hsia\",\"doi\":\"10.1109/RELPHY.2007.369882\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The integration of copper (Cu) and low-k dielectrics has posed challenges for stress migration (SM) reliability. Besides process tuning, design for manufacturability (DFM) approach is proposed to suppress stress-induced void failures. In this paper, a three-dimensional (3D) finite element analysis (FEA) simulation model was used to identify the main mechanisms of several key processes and design approaches responsible for SM reliability improvement reported in the literature. On the basis of understanding the critical parameters and design/structural weak points affecting SM reliability, DFM is proposed to enhance the SM reliability of future nanoscale technologies employing porous ultra low-k dielectrics. The study illustrates the importance of process and design interactions to make porous ultra low-k Cu interconnects more resilient to SM degradation for future CMOS technologies.\",\"PeriodicalId\":433104,\"journal\":{\"name\":\"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2007.369882\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2007.369882","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

铜(Cu)和低k介电体的集成对应力迁移(SM)的可靠性提出了挑战。除了工艺调整外,还提出了可制造性设计(DFM)方法来抑制应力引起的空洞破坏。本文采用三维有限元分析(FEA)仿真模型,确定了文献报道的SM可靠性改进的几个关键过程和设计方法的主要机制。在了解影响SM可靠性的关键参数和设计/结构弱点的基础上,提出了DFM以提高未来纳米级多孔超低k介电体技术的SM可靠性。该研究说明了工艺和设计相互作用的重要性,以使多孔超低钾铜互连在未来的CMOS技术中更具抗SM退化的弹性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design for Manufacturability and its Role in Enhancing Stress Migration Reliability of Porous Ultra Low-k Copper Interconnects
The integration of copper (Cu) and low-k dielectrics has posed challenges for stress migration (SM) reliability. Besides process tuning, design for manufacturability (DFM) approach is proposed to suppress stress-induced void failures. In this paper, a three-dimensional (3D) finite element analysis (FEA) simulation model was used to identify the main mechanisms of several key processes and design approaches responsible for SM reliability improvement reported in the literature. On the basis of understanding the critical parameters and design/structural weak points affecting SM reliability, DFM is proposed to enhance the SM reliability of future nanoscale technologies employing porous ultra low-k dielectrics. The study illustrates the importance of process and design interactions to make porous ultra low-k Cu interconnects more resilient to SM degradation for future CMOS technologies.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信