{"title":"A fully integrated 0.18-/spl mu/m CMOS low noise amplifier for 2.4-GHz applications","authors":"Yu-Shing Shen, Huazhong Yang, Rong Luo","doi":"10.1109/ICASIC.2005.1611397","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611397","url":null,"abstract":"A low noise amplifier (LNA) with good linearity and low noise figure has been designed by 0.18/spl mu/m CMOS technology for 2.4GHz applications. The amplifier provides IIP3 of 11.8dBm and input -1dB compression point (CP) of -13.5dBm with a noise figure equal to 2.77dB, and has a forward gain of 4.5dB and power dissipation of 18mW using 1.8V supply.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125469958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Feipeng Huang, Yumei Huang, Dedong Ze, Zhiliang Hong
{"title":"A method to effectively decrease the settling time of gain-boost OTA","authors":"Feipeng Huang, Yumei Huang, Dedong Ze, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611350","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611350","url":null,"abstract":"A method was proposed to decrease the settling time of gain-boost folded cascode operational trans-conductance amplifier (OTA). Through the small-signal analysis of gain-boost OTA, the expression of pole and zero was attained successfully; then the effect of pole-zero (doublet) on settling time was revealed fully. To reduce its effect, a method was finally proposed that the unity-gain frequency (omegaur) of regulation amplifier should be a little larger than the unity-gain frequency (omegauc) of core amplifier. This method was proven to be effective by simulation result","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126624163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RTL satisfiability solving using an ATPG based approach","authors":"Min-Chuan Chen, Weimin Wu, Jinian Bian","doi":"10.1109/ICASIC.2005.1611475","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611475","url":null,"abstract":"We present a special approach to solving satisfiability problem in RTL (register transfer level) circuit, which contains both Boolean logics and word-level arithmetics. In our approach, an ATPG (automatic test pattern generation) based satisfiability solver is implemented on RTL netlist model. As expert tool for circuits, our ATPG engine employs fast constraint propagation, where all the signals are treated as integers. For the undecided signals, we render a depth-first search. The huge search space is cut down by some heuristics. Experimental results on ITC benchmarks demonstrate the feasibility and efficiency of our techniques.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"86 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Datapath verification with SystemC reference model","authors":"Dongjun Lou, J.S. Yuan, Daguang Li, C. Jacobs","doi":"10.1109/ICASIC.2005.1611474","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611474","url":null,"abstract":"Bit-level hardware description language (HDL), such as Verilog or VHDL, has its interior problems to describe complex math formulas in register transaction level (RTL). Its Boolean solutions lead to the necessity of complex controls for math operations, and often result in poor performance for datapath verification. Instead of solving the problem at the bit-level, a method of SystemC reference model (SCRM) is proposed to aid conjunctions of bitvector manipulations in RTL into arithmetic number operations in SystemC, which helps to verify the datapath design automatically. The application experience of SCRM in our digital still camera SoC shows that it is much more efficient and thorough to verify the datapath with the assistance of cycle accurate SystemC models realtimely, than previously manual verification","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel asynchronous multiple function multiply-accumulator","authors":"Jian Gao, Jing Chen","doi":"10.1109/ICASIC.2005.1611253","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611253","url":null,"abstract":"The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123069983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"To improve the voice quality over IP using channel coding","authors":"R. Agrawal, N. Gupta","doi":"10.1109/ICASIC.2005.1611278","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611278","url":null,"abstract":"Voice over Internet protocol (VoIP) is the transmission of voice over networks using the internet protocol. IP networks have become increasingly popular in the past few years, due to the exponential growth of the public internet leading the way in to the IP world. Long distance calls, especially international subscriber dialing (ISD), can be made significantly less expensive when supported by an IP network rather than by the PSTN. Any call made is supported by VoIP technology and it involves the transmission of many individual packets over an IP network. Thus the cost of VoIP calls in part depends on the number and size of packets that must be transmitted. So voice (source) compression technology is used to reduce the amount of bandwidth required in order to reduce cost and to reduce the delay impact from network. But, compression techniques increase the network impairments also. When packets are transmitted through network they are affected by impairments, like packet drop and end-to-end delay. The main agenda of VoIP service providers is to provide good quality of service (QoS). The objective of this research work done is to minimize, the error introduced in channel due to the above mentioned network impairments and hence improve the quality of sound, and also analyze the voice quality with and without use of channel coding scheme. There are two measuring techniques, subjective and objective. In subjective method we measure the mean opinion score (MOS) and use matching algorithms in objective methods to measure the difference between decoded outputs of source coding system and joint source-channel coding system. In this work, the objective method is used and it is observed that the performance of the system improves significantly","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"136 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125817094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 40dB, 100MHz CMOS IF variable gain amplifier for DVB-C receivers","authors":"Ting-Hua Yun, Li Yin, S. Tang, Jianhui Wu","doi":"10.1109/ICASIC.2005.1611362","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611362","url":null,"abstract":"A CMOS IF VGA used for DVB-C receivers is presented in this paper. The VGA core is based on current-steering structure, and several optimization methods are used to improve the linearity and stability. A novel CMOS exponential voltage generator is designed to realize the linear-in-dB control characteristic. The simulation results based on 0.25 mum CMOS process indicate that the VGA can provide 40dB gain control range, the IIP3 at the minimum gain setting 17.2 dBm, and the minimum NF 7.8 dB. The overall current dissipation is less than 23 mA at 3.3V supply voltage","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124988324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VLSI architectures of domain adaptive fuzzy logic system","authors":"Zhang Xun, Wang Peng, Jin Dong-ming","doi":"10.1109/ICASIC.2005.1611314","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611314","url":null,"abstract":"A novel domain adaptive fuzzy logic controller is presented in this paper, which adds a domain adaptive structure on the architecture of an original fuzzy logic controller. It saves the hardware consumption, and accelerates the system convergence. The domain mapping fuzzy logic controller is successfully applied to control the inverted pendulum on a hardware test-bed. The theory and optimization of the method are also discussed. According to this strategy, a circuit can generate domain mapping gene is realized by CSMC 0.6mum mixed-signal technology. This approach provides a valuable theory basement to the implement of self-adaptive fuzzy controller hardware chip","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121478481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect delay optimization using a novel hybrid insertion strategy","authors":"Xiangyuan Liu, Shuming Chen","doi":"10.1109/ICASIC.2005.1611441","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611441","url":null,"abstract":"Interconnection techniques play an important role in the growth of semiconductor industry into future generations. A novel hybrid insertion strategy based on repeaters and low-swing differential-signaling circuits for global interconnect is presented in this paper. It takes advantage of those circuits on driving long wires in different length, and optimally inserts them along the wires. Simulation results using HSPICE for 0.18mum process show that delay, energy, energy-delay-product (EDP) and area are considerably decreased compared with other strategies available. Moreover, it is very suitable for integration in an EDA tool flow and helpful to the reuse of low-swing differential-signaling circuits","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125121252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An optimization of VLSI architecture for DFE used in Ethernet","authors":"Wang Xuejing, Ye Fan, R. Junyan","doi":"10.1109/ICASIC.2005.1611261","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611261","url":null,"abstract":"An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18/spl mu/m CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"24 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
