{"title":"一种新型异步多函数乘法累加器","authors":"Jian Gao, Jing Chen","doi":"10.1109/ICASIC.2005.1611253","DOIUrl":null,"url":null,"abstract":"The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A novel asynchronous multiple function multiply-accumulator\",\"authors\":\"Jian Gao, Jing Chen\",\"doi\":\"10.1109/ICASIC.2005.1611253\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611253\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel asynchronous multiple function multiply-accumulator
The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.
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